This article presents a case study involving flash memory bit failures characterized by threshold voltage changes due to positive gate disturb stress. An inconsistency in failing bit behavior, which was found to be dependent on the test mode, was explored to provide an electrical explanation for the failure. The underlying defect was isolated and subsequently identified by physical analysis.

This article presents a nanoprobing method that uses high-speed pulses to characterize in-die SRAM bit cells. The authors describe the basic setup of the test system and demonstrate its use on a six-transistor bit cell failure. The method reduces fault localization time and decreases the possibility of deprocessing past the fail because testing is done at metallization layer 1. The bit’s reaction is captured in the form of analog current measurements, resulting in a unique signature of the failure.

Selecting a fault isolation technique for a particular type of SRAM logic failure requires an understanding of available methods. In this article, the authors review common fault isolation techniques and present several case studies, explaining how they determined which technique to use.

Probing in the sub-100 nm realm requires new tools and techniques that are relatively easy to learn if users follow the advice of the authors of this article. The authors present a probing method based on scanning probe technology and demonstrate its use on a 90-nm transistor failure due to a poly-silicon gate short. They also address challenges associated with sample preparation, probe tip contamination and wear, and the effects of vibration and drift.

Scanning capacitance microscopy (SCM) and nanoprobing are key tools for isolating and understanding transistor level fails. In this case study, SCM and nanoprobing are used to determine the electrical characteristics of cluster-type failures in 14 nm SOI FinFET SRAM after standard FIB cross-section imaging failed to reveal any visible defects.

This article discusses the advantages of SEM-based nanoprobing and the various ways it can be used to locate defects associated with IC failures. It describes the basic measurement physics of electron beam induced current, absorbed electron, and voltage distribution contrast imaging and presents examples showing how the different methods are used to isolate low- and high-resistance sites, shorts, and opens as well as ion implantation and metal patterning defects.

Sandia National Laboratories manufactures 0.5 µm CMOS ICs using local oxidation of silicon (LOCOS) and shallow trench isolation (STI) technologies. A program based on burn-in and life tests is being used to qualify the process for military and space applications. Representative ICs from baseline wafer lots are assembled in ceramic packages and electrically tested before, during, and after burn-in and subsequent life tests. Two types of ICs are being used for this qualification, a 256K-bit SRAM and a microcontroller core. More than 600 ICs have passed qualification tests with very few failures, although recently, a group of SRAMs from a development wafer lot incorporating nonqualified processes had an usually high number of failures during their initial electrical test after packaging. This article describes the investigation that was conducted to determine the cause of these failures.

Scan chains help detect and identify failures in integrated circuits, but they are also susceptible to failure themselves. When scan chains break, it does not necessarily render them useless. Normally, scan chains can be debugged and diagnosed so that they can be fixed or used while masking out vector bits associated with broken or corrupted portions of the chain. This article describes the different ways that scan chains can break and how it tends to affect their performance. It explains how to repair various types of scan chain failures or at least regain partial use for limited testing purposes.

Parametric analysis of SRAM cells is widely used to locate faults and analyze device failures, but the pico-probing and bit-line multiplexing required for data acquisition is becoming increasingly difficult. This article explains how the addition of an on-die low-yield analysis circuit eliminates the problem. The simplicity of the measurement circuit and the potential to use a known library of curves, makes low-yield analysis one of the most versatile DFT techniques for cache fault isolation.

This article describes how physical attacks can be launched on different types of nonvolatile memory (NVM) cells using failure analysis tools. It explains how the bit information stored inside these devices is susceptible to read-out and fault injection attacks and defines vulnerability parameters to help quantify risks associated with different modalities of attack. It also presents an in-depth security analysis of emerging NVM technologies and discusses potential countermeasures.

Voltage contrast followed by electron beam induced current imaging is an effective approach for isolating IC failures. This article briefly reviews the physics of signal generation for both techniques and presents several examples illustrating how this powerful combination contributes to advanced defect localization.

Various NVM technologies are being explored for neuromorphic system realization, including resistive RAM, ferroelectric RAM, phase change RAM, spin transfer torque RAM, and NAND flash. This article discusses the potential of RRAM for such applications and evaluates key performance and reliability metrics in the context of neural network image classification. The authors conclude that the accuracy-power tradeoff may be further improved using alternative material stacks and multi-layer dielectrics so as to achieve better control of the oxygen vacancy or metallic filamentation process that governs RRAM switching characteristics.

This article describes a hardware metering fingerprint technique, called the memometer, that addresses supply chain integrity issues with field-programmable gate arrays (FPGAs). The memometer is a physically unclonable function (PUF) based on cross-coupled lookup tables that overcomes manufacturing memory power-on preset. The fingerprints are not only unique, but also reliable with average hamming distances close to the ideal values of 50% (interchip) and 0% (intrachip). Instead of having one fingerprint per device, the memometer makes provision for hundreds with the potential for more.

This article presents an automation workflow for the development of analog and mixed-signal devices similar to the two-stage process used for the design and verification of logic ICs. The use of a co-simulation interface makes it possible to build and verify failure models.

This editorial discusses the emergence of chiplets and its potential impact on IC design, fabrication, and failure analysis.

This is the second article in a two-part series on test-based failure analysis (TBFA). The first article, which appeared in the August 2001 issue of EDFA, discussed the need for automated diagnostics and the general concept of TBFA. This article discusses the steps involved in implementing a TBFA process and addresses the challenges that are likely to be encountered. It explains how to gather data required to link observed behavior to specific faults, how to set up and use fault dictionaries, and how to handle unmodeled as well as bridging faults. It also discusses the use of TBFA with conventional voltage and quiescent current (IDDQ) testing.

This article reviews recent work aimed at characterizing soft-error effects in SRAM circuits fabricated with bulk silicon FinFETs. Accelerated tests were conducted on 6T planar and FinFET-based SRAM cells by exposing them to high-energy neutrons and alpha particles. Based on test results and simulations, the authors show that soft-error rates are much lower in FinFET devices because the geometry of the fins limits charge collection.

Three case studies involving 14 nm SRAM technology show how progressive FIB cross-sectioning and top-down analysis can be supplemented with nanoprobing and TEM tomography to determine the root cause of failure. In the first case, the memory failure is traced to an abnormal gate profile. In the second case, the failure is attributed to a metal line short, and in the third case, a gate defect.

Analog computing is an important step in taking neural net processing to the next level. However, as this column explains, reliability is intimately linked to performance and efficiency in analog systems, more so than in any modern digital system, and further work is required to understand the relationship.

This article provides a high level overview of high speed analog circuits and associated failure analysis techniques. It discusses the failure modes and mechanisms of voltage reference circuits, high speed op amps, and digital-to-analog and analog-to-digital converters, the fundamental building blocks used to create high speed analog devices. It also explains how to deal with difficulties involving circuit node access, circuit loading, and performance.