Search Results for ball grid arrays

This article is the first in a two-part series analyzing solder connection failures between BGA packages and PCB assemblies. Part I examines failures attributed to oxygen intrusion during reflow, underetched solder resist, and solder paste printing problems. In the latter case, X-ray inspection revealed no abnormalities other than a variation in ball size. To get to the root cause, the corpus of the BGA was progressively ground away, leaving only the balls and an unobstructed view of the PCB surface. A description of the process, supported by detailed images, is included in the article. In Part II, scheduled for the May 2017 issue of EDFA, the author delves deeper into the analysis of voids and presents an alternate FA approach that involves grinding away much of the PCB.

This is the second article in a two-part series investigating solder connection failures associated with BGA packages. Part I, in the February 2017 issue of EDFA, examines various cases of open and short circuit failures, discusses the formation of voids, and explains how to reveal important clues by grinding away the BGA package. Part II continues the analysis of voids and focuses in on failures due to circuit board faults. In such cases, the board is ground away from the backside, stopping just short of the first inner copper layer. The alignment of the two uppermost copper layers, the integrity of microvias, and other potential problems are then examined using polarized light which readily passes through the remaining resin and fibers. As the examples in the article show, this approach can reveal a wide range of manufacturing defects in PCBs.

The influence of electric current flow and electrically induced Joule heat on thermal stress for weld joint cracks at both interfaces is still not fully comprehended. This article investigates the effect of subjecting the ball grid array package to a cyclic current input. Current density, Joule effect, and temperature curves are examined.

A deep learning-based nondestructive approach for void segmentation in BGA solder balls using 3D x-ray microscopy is presented.

This article presents best practices and procedures for analyzing printed circuit board assembly failures. It discusses the role of electrostatic discharge and electrical overstress, the increasing complexity of ball grid arrays and buried vias, the challenges associated with lead-free solder processes, and the problems caused by counterfeit components flowing into our supply lines. It also includes a summary of the tools available to failure analysts and how they are best put to use

This article discusses the failure analysis challenges associated with large overmolded 2.5D packages and explains how laser decapsulation followed by microwave-induced plasma (MIP) spot etching removes overmold while keeping everything else intact. It also describes a defect isolation procedure in which the sample is analyzed in a large chamber environmental SEM with its ball grid array directly wired to an EBAC amplifier.

With the July 2006 implementation of RoHS (the restriction of the use of certain hazardous substances in electrical and electronic equipment), the electronics reliability industry has seen a changeover to lead-free solders and “green” mold compounds that have no bromine- or antimony-based flame retardants. This article addresses some of the challenges caused by implementation of the new requirements.

This column addresses the importance of information exchange among failure analysts and explains how it can be accomplished.

Chip-scale packages (CSPs) make efficient use of space on PCBs, but their small size, multilevel stacking arrangements, and complex interconnects present serious challenges when it comes to testing and failure analysis. This article describes some of the problems encountered when dealing with various types of CSPs and provides practical solutions based on the tools and techniques available in most FA labs. It discusses the causes and effects of package and die related failures and walks readers through the steps involved in decapsulating plastic FBGA packages using conventional etching, polishing, and milling techniques. It also includes a case study involving a failure caused by improper laser marking.

Electronic components and assemblies are subjected to temperature variations at every stage of life, resulting in the buildup of internal stress. This article explains how such stress contributes to failures and introduces a measurement technique that allows users to visualize stress distributions and assess their effects on lifetime and reliability. Application examples illustrating the capabilities of the new topography and deformation measurement approach are also presented.

This article discusses the concept of a virtual known good device (VKGD) and how it used in the development of advanced 3D packaging. It explains that a VKGD is essentially an electromagnetic model of an IC package, including bumps, interposers, and through-silicon vias. These models, used in conjunction with reflectometry data, help engineers isolate faults in the early stages of IC package development, greatly reducing cycle times.

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.

This article presents two case histories that shed light on the role of gold in lead-free solder joint failures and the damage mechanisms involved. One of the failures, a brittle fracture of the solder joint, is attributed to the synergistic effects of voids, intermetallic compounds, and CTE mismatch. The investigation of the other failure revealed evidence of tin-whisker formation. As the author explains, the growth of tin whiskers is due to compressive stress in the tin solder material caused by diffusion of end-cap metals (Ni and Cu) and the formation of Sn-Ni-Au intermetallics. In both cases, the failures can be prevented by limiting the thickness of gold on all components.

Chip-scale packages (CSPs) make efficient use of space on PCBs, but their small size, multilevel stacking arrangements, and complex interconnects present serious challenges when it comes to testing and failure analysis. This article describes some of the problems encountered when dealing with various types of CSPs and provides practical solutions based on the tools and techniques available in most FA labs. It discusses the causes and effects of package and die related failures and walks readers through the steps involved in decapsulating plastic FBGA packages using conventional etching, polishing, and milling techniques.

The Assembly Analytical Forum (AAF) is an organization under the auspices of the Sematech Quality Council. The AAF charter is to develop Packaging Analytical Roadmaps five to ten years into the future that are consistent with the International Technology Roadmap for semiconductors (ITRS). At ISTFA 2003, the AAF will convene with interested conference attendees to review, edit, and validate a white paper that will quantify critical gaps in the current suite of test, measurement, and characterization tools used in the semiconductor industry and provide recommendations on how to address them. The intent is to update the document biannually and review it in numerous industry venues to ensure its relevancy and utility. This article is somewhat of a preview to the Rev 0 AAF white paper.

Integrated circuits are subjected to various forms of friction during fabrication and packaging, creating potential problems due to the buildup of charge. This article looks at the distinct characteristics of triboelectric charging damage on silicon-on-insulator devices at the wafer and package level. Telltale signs of this type of damage include spatial dependency, distinct TIVA-signal patterns, and bimodal static current distributions with significant changes after burn-in.

This article describes a proposed novel metric to furnish chip designers with a prognostic tool for x-ray imaging in the pre-silicon stage. This metric is fashioned to provide designers with a concrete measure of how visible the fine-pitched features of their designs are under x-ray inspection. It utilizes a combination of x-ray image data collection, analysis, and simulations to evaluate different design elements.

This is the second article in a two-part series on how to properly thin curved and highly warped die. Part I, published in the August 2015 issue of EDFA , introduces the concept of contour machining, a CNC technique driven by thickness measurement data, and describes a multistep grinding and lapping process along with the results. Part II covers the mechanical, physical, and mounting variables associated with thinning and polishing, giving particular attention to mounting procedures and their effect on surface profiles and thickness variations.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

Over the last few years, new challenges increased the pressure on packaging and assembly analytical resources. Reduced product development cycle time, increased market segmentation, new package and die level materials, ever shrinking device geometries, and fully enabled technologies (i.e. with thermal, retention, and EMI solutions) created these new pressures on fault isolation/failure analysis efforts and package development.