Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.

Semiconductor trends, as embodied in the International Technology Roadmap for Semiconductors (ITRS), provide a guide for the challenges facing the failure analysis community. This process is a risk assessment of key features forecast for the impact of future technologies on failure analysis. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are largely driven by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The industry paths for addressing these challenges are discussed.

The Product Analysis Forum (PAF), sponsored by the Quality Council of SEMATECH, has been chartered to facilitate the ongoing development of tools and techniques for semiconductor characterization and failure analysis. Drawing on input from industry experts, universities, and national laboratories, the PAF has identified critical needs in three areas: software fault isolation, backside fault isolation, and deprocessing & inspection. This article discusses the current state of deprocessing and inspection technology and provides insights into how some of the future challenges will be addressed.

This article discusses the current state of large area integrated circuit deprocessing, the latest achievements in the development of automated deprocessing equipment, and the potential impact of advancements in gas-assisted etching, ion source alternatives, compact spectroscopy, and high-speed lasers.

The 39th International Symposium for Testing and Failure Analysis (ISTFA 2013) was held in San Jose, Calif., November 3-7, 2012. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, User’s Group meetings, and equipment exposition.

A review of the 2001 edition of the International Technology Roadmap for Semiconductors indicates major obstacles ahead. Of the three basic failure analysis steps—inspection, deprocessing, and fault isolation—the latter is the most at risk, especially physical fault isolation.

The shrinking geometries in today’s 3-D integrated circuit (IC) designs generate an urgent need for a variety of tools to isolate failures on advanced semiconductor devices. There has been no single technique that adequately addresses all types of failures with the required fast cycle time. Complex failures that are not resolved by the faster global approaches are best addressed by probing technologies, where waveforms or voltages are measured from node to node. These approaches are time-consuming and usually require detailed understanding of the circuit operation. Global techniques that map the secondary effects of defects have been widely used for as many failures as possible. These secondary effects include thermal emission, photon emission, and circuit operation dependencies on localized heating or carrier generation at a defect site. Each technique addresses some segment of the failure mechanisms, but none is universally effective in itself. The use of thermal emission techniques has waned due to the issues of lower power supply voltages, which result in poor sensitivity for older techniques and decrease in minimum resolved feature sizes.

The 43rd International Symposium for Testing and Failure Analysis (ISTFA 2017) was held in Pasadena, Calif., November 5-9, 2017. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, and User’s Group meetings.

This column discusses the potential benefits of developing a dedicated synchrotron-based tool suite for advanced, high-throughput characterization, deprocessing, and validation of ICs.

This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.

Recent work with a commercial instrument based on a SQUID sensor shows that magnetic field imaging can be very effective in isolating defect shorts in packages and dies. This technique is especially beneficial when the defect is buried under layers of metal, Si, or encapsulation materials. Many of these defects can be imaged for coarse localization without any deprocessing of the sample. SQUID sensors can produce weak current images even in the presence of background current five orders of magnitude stronger. This high sensitivity also enables effective imaging with much lower currents than thermal techniques.

Off-axis electron holography is a TEM-based imaging technique that reveals dopant anomalies and junction profiles in semiconductor devices. This article explains how the method works and how it is being used to visualize transistor source-drain regions, diffusion-related defects, and other features of interest in TEM samples. It also discusses related challenges and compares off-axis electron holography with other profiling techniques, particularly junction staining.

A new way to detect gate oxide defects has been developed. The method, as the article explains, is based on wet chemical etching and is particularly effective for devices with floating gates. Test samples with exposed poly-Si gates are placed in a KOH:H 2 O solution and a voltage is applied to the silicon substrate. At a certain voltage, normal gates begin to etch, while those shorted to the substrate through gate oxide defects develop an anodic oxide and thus remain unetched. This method has proven effective in assessing gate oxide integrity without direct observation of the oxide, which requires complicated deprocessing and a lot of time. It also reveals electrical characteristics of gate oxides that are difficult to identify by conventional physical analysis.

This article provides a summary of the presentations given at the four User’s Group meetings at ISTFA 2012. Each user group focused on one of the following topics: nanoprobing, contactless fault isolation, focused ion beam, and sample preparation.

This column discusses the basic knowledge and skills needed by failure analysis engineers, with a focus on problem-solving ability.

This column provides some thoughts on the cultivation of ideas and the conditions that must exist in a failure analysis laboratory to allow fledgling methods to become deeply rooted, flourishing techniques. As an example, the author recounts the introduction and subsequent development of resistive interconnect localization (RIL) is his lab.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

Selecting a fault isolation technique for a particular type of SRAM logic failure requires an understanding of available methods. In this article, the authors review common fault isolation techniques and present several case studies, explaining how they determined which technique to use.

This article presents a complete business model for Failure Analysis (FA) as a high tech provider in the world of microelectronics. Part I introduces the fundamentals of such a model. It starts with the definitions of a business process, and then the analysis flows are presented. Finally, a Key Performance Indicator (KPI) based operation is developed. Part II of this article will appear in the next issue of EDFA, and it will address the implementation of such a model in an FA lab. It discusses the interdependencies of workload and cycle times—the pipeline management. This opens the path to quantitative target setting agreements with customers. A complete system builds a database that can calculate all the parameters for an FA lab tailored exactly to the demand of the customer. Such a database acts as a reference lab and represents best FA practice.