Search Results for automated thinning

Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.

This article describes an automated sample preparation process for SEM and TEM analysis based on submicron polishing. The method uses robotics, image processing, and a polishing wheel under computer control for a fully automated recipe-driven process that creates exact cross-sections with 0.1 μm accuracy.

Recent developments in automated image acquisition and metrology using transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) have significantly improved the speed, precision, and usability of these techniques for controlling advanced semiconductor device manufacturing processes. As device dimensions have continued to shrink, these techniques may be needed to replace scanning electron microscopy (SEM) for the smallest critical dimension (CD) measurements. This article describes the use of automated S/TEM in a high-throughput CD-metrology workflow to support process development and control and explains how automated sample-preparation, data-acquisition, and metrology tools increase both throughput and data quality.

An optically polished silicon surface with controlled sample thickness is the key to successful backside imaging. Achieving that manually can be very difficult in cases where ICs are encapsulated in packaging materials. This article describes the challenges involved with traditional (manual) backside silicon sample preparation techniques and the improvements obtainable with automation.

With the growing complexity of new processes and the introduction of new materials, the need for product yield management and process control is placing unprecedented demands on failure analysis laboratories in the semiconductor industry. These demands are calling for faster and superior analytical capabilities to determine root-cause failure mechanisms in semiconductor devices fabricated using deep submicron processes. This article presents a new automated sample preparation technique that facilitates direct electrical contact to the area of interest, with a surface quality sufficient for scanning probe microscope analysis.

This article discusses the current state of large area integrated circuit deprocessing, the latest achievements in the development of automated deprocessing equipment, and the potential impact of advancements in gas-assisted etching, ion source alternatives, compact spectroscopy, and high-speed lasers.

Automation may be responsible for the loss of many jobs, but it has been and is likely to remain more of a help than a threat to semiconductor failure analysts.

This article describes recent advancements in multi-probe sensing schemes and development of a tomographic atomic force microscopy tool for materials research and failure analysis.

The Electronic Device Failure Analysis Society established the Die-Level Post-Isolation Domain Council to provide an overview of the upcoming challenges in this area and guide technique developments for next-generation analytical tools. This column summarizes the findings of the council in the areas of sample preparation, microscopy, nanoprobing, circuit editing, and scanning probe microscopy. It is a preview of the full roadmap document, which is in preparation to be released to the EDFAS community.

This article, the first in a multi-part series, describes how to finely control remaining silicon thickness (RST) through the correction of mechanical surface profiles using multipoint thickness measurements. It explains why multipoint thickness measurements are necessary and discusses the realities of silicon thickness measurements. With careful processing, cleaning, and RST measurements, samples can be reliably processed to a 50 μm thickness with a variation of +/- 2.5 μm across the majority of the die.

Scan-based diagnostics produce high-confidence target lists of suspected faults associated with electrical fail signatures. Physical coordinates extracted from these lists serve as a guide for physical failure analysis. When certain conditions are met for the design database and pattern sets, the extraction can be automated and the analysis completed within minutes. The logic mapping flow is a natural extension of scan-based diagnosis with the potential to reach new levels of electrical failure analysis without the extensive data collection and resources associated with signature analysis. This article describes the logic mapping concept and how to implement the flow. It also presents the results of actual cases in which logic mapping was used.

In this article, the authors evaluate micro CNC milling as an alternative to manual parallel lapping for mechanical cross-sectioning of flip-chip packaged samples. They describe both processes, and how they compare to other cross-sectioning techniques, and clearly illustrate the differences. SEM images of a manually polished sample show process-induced cracking, chipping, and delamination at the die-C4 interface. In contrast, the CNC-milled sample is artifact-free and the C4 bumps are uniformly exposed along the entire length of the cross-section.

The sixth FIB-SEM workshop was held March 1, 2013, in Cambridge, Mass. This article provides a summary of the event along with highlights from the 18 paper presentations.

Many standard physical failure site isolation techniques require an electrical stimulus to drive test devices into a failing condition. This function has been provided by bench test electronics for some time, but increasing device complexity is causing a migration to more sophisticated equipment such as pattern generators and logic analyzers. In anticipation of further increases in pin count and density, a new class of small footprint testers is emerging. These portable systems, called ASIC verification testers, facilitate the transfer of ATE test programs to failure analysis laboratories at relatively low cost.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.

This column discusses the potential benefits of developing a dedicated synchrotron-based tool suite for advanced, high-throughput characterization, deprocessing, and validation of ICs.

Transmission electron microscopy (TEM) plays an important role semiconductor process development, defect identification, yield improvement, and root-cause failure analysis. At the same time, however, certain artifacts of specimen preparation and imaging present barriers for linear scaling of TEM techniques. This article assesses these challenges and explains how electron tomography is being used to overcome them.

This article discusses recent improvements in FIB circuit edit as well as general uses and optimization techniques.

This column is part of a series of reports on the findings to date of the EDFAS Failure Analysis Roadmap Councils. The Failure Analysis Future Roadmap Council (FAFRC) is concerned with identifying the longer term needs of the FA community. This article discusses analysis challenges associated with the growing number of elements being incorporated into integrated circuit fabrication. It includes tables summarizing top challenges in front end and package analysis.

This article provides a brief overview of STEM-in-SEM, discussing the pros and cons, recent advancements in detector technology, and the emergence of 4D STEM-in-SEM, a relatively new method that uses diffraction patterns recorded at different raster positions to enhance images offline in selected regions of interest.