Search Results for artificial intelligence computing

The electronic device failure analysis community will be instrumental in successfully guiding the industry's transformation in reponse to demand for artificial intelligence capabilities. This editorial outlines the challenge and how the FA community can help address growing needs in this technical area.

This article provides a systematic overview of knowledge-based and machine-learning AI methods and their potential for use in automated testing, defect identification, fault prediction, root cause analysis, and equipment scheduling. It also discusses the role of decision-making rules, image annotations, and ontologies in automated workflows, data sharing, and interoperability.

This column assesses the near-term challenges associated with quantum computing, noting that 15 years is an optimistic estimate for commercially viable quantum cloud computing. In the midst of the struggle, however, there is also opportunity, particularly in metrology and component development.

This column explains how machine learning is being used to diagnose electrical faults and identify potential hot spots and systematic defects during IC design.

The 45th International Symposium for Testing and Failure Analysis (ISTFA 2019) was held in Portland, Oregon, November 10-14, 2019. This article gives a brief summary of the highlights and identifies key contributors to the event. It also includes highlights of panel discussions from the inaugural meeting of Women in Electronics Failure Analysis (WEFA) and the panel discussion "What Does Artificial Intelligence Mean to Failure Analysis Engineers?" The article concludes with a brief recap of each of the four User Group meetings that took place during the conference: Sample Prep, System on Package, FIB/Circuit Edit, and Nanoprobing.

Automation may be responsible for the loss of many jobs, but it has been and is likely to remain more of a help than a threat to semiconductor failure analysts.

This article provides a recap of the 50th International Symposium for Testing and Failure Analysis (ISTFA), which was held in San Diego from October 28 to November 1, 2024. It includes General Chair Yan Li’s wrap-up, a list of the winning ISTFA papers and posters, and highlights from panel sessions and user group meetings.

Trapped ion systems are one of the leading technology platforms for quantum computing. This article describes the construction and operation of ion trap devices and the various modes of failure that have been observed. Examples of failure in either the rendering or use of packaged trap chips are presented, including electrode shorts and opens, detached bond wires, and RF breakdown damage.

This article proposes the MicroStructural Hierarchy Descriptor (µSHD) as a systematic and quantitative approach to spectra and image data in microelectronics failure analysis. It discusses concrete routes for employing µSHD directly as the quantitative descriptor for supervised and unsupervised machine learning. The authors propose that µSHD tools can be used to automate and improve characterization techniques and image processing and analysis protocols.

This column is part of a series of reports on the findings to date of the EDFAS Failure Analysis Roadmap Councils. The Failure Analysis Future Roadmap Council (FAFRC) is concerned with identifying the longer term needs of the FA community. This article discusses analysis challenges associated with the growing number of elements being incorporated into integrated circuit fabrication. It includes tables summarizing top challenges in front end and package analysis.

The EDFAS Die-Level Roadmap Committee was formed to identify forthcoming challenges related to electrical fault isolation within the next five years and collaborate with various stakeholders, including industry, academia, and tool vendors, to devise practical solutions. To that end, the team has pinpointed five critical areas of focus: (1) laser-based, photon emission, and thermal; (2) 2D/2.5D/3D packaging; (3) product yield, test, and diagnostics; (4) general (leading edge technologies); and (5) system level, analog/RF, and digital functional.

A deep learning-based nondestructive approach for void segmentation in BGA solder balls using 3D x-ray microscopy is presented.

Advanced 10 nm device delayering is a critical process for verifying and validating the circuit design layout and extracting the structures buried inside the chip. The work featured in this article takes advantage of chemically assisted focused ion beam processing with ultraviolet spectroscopy to destructively delayer integrated circuits starting from the shallow trench isolation layer, enabling high-resolution SEM imaging at each layer.

This article shows how 3D XRM can be applied to nondestructively detect non-optimized assembly processes that can influence local stresses and overall device reliability. This makes it useful for process development and failure analysis. When used along with AI training models, 3D XRM can achieve analysis of highly integrated packaging structures with reasonable throughput for process validation and error correction guidance.

This article proposes a design for a real-time Trojan detection system and explores possible solutions to the challenge of large-scale SEM image acquisition. One such solution, a deep-learning approach that generates synthetic micrographs from layout images, shows significant promise. Learning-based approaches are also used to both synthesize and classify cells. The classification outcome is matched with the design exchange format file entry to ensure the purity of the underlying IC.

This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.

The high energy-resolving power of superconducting x-ray detectors reduces unwanted x-ray backgrounds, uses x-ray photons efficiently, and allows for discrimination among multiple chemical elements in a sample. This article discusses the challenges of analyzing the internal structure and composition of integrated circuits, and how 3D imaging can benefit manufacturers and researchers. It covers the development of superconducting x-ray sensors, their advantages over traditional sensors, potential applications, and focus areas for future work to develop this technology.

This article presents a recent breakthrough in the use of machine learning in semiconductor FA. For the first time, cell-internal defects in FinFETs have not only been detected and diagnosed, but also refined, clarified, and resolved using cell-aware diagnosis along with root cause deconvolution (RCD) techniques. The authors describe the development of the methodology and evaluate the incremental improvements made with each step.

This article describes a proposed novel metric to furnish chip designers with a prognostic tool for x-ray imaging in the pre-silicon stage. This metric is fashioned to provide designers with a concrete measure of how visible the fine-pitched features of their designs are under x-ray inspection. It utilizes a combination of x-ray image data collection, analysis, and simulations to evaluate different design elements.

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.