Electromigration is a wearout mechanism that contributes significantly to IC failures. This article discusses the causes and effects of this often overlooked failure mode and presents practical guidelines to help analysts determine whether or not electromigration is the cause of a particular failure. It also discusses the differences between aluminum and copper electromigration.

Stress voiding has re-emerged as a concern in advanced metal systems with their reduced dimensions and multilayer designs. Unless analysts are familiar with the physics and history of stress voids in ICs, chances are they will go unnoticed. This article discusses the basic cause of stress cracks and the clues that give them away.

Resistive interconnections, a type of soft failure, are extremely difficult to find using existing backside methods, and with flip-chip packages, alternative front side approaches are of little or no help. In an effort to address this challenge, a team of engineers developed a new method that uses the effects of resistive heating to directly locate defective vias, contacts, and conductors from either side of the die. In this article, they discuss the basic principles of their new method and demonstrate its use on two ICs in which a variety of resistive interconnection failures were found.

This article discusses the latest trends in wire bonding and examines common failure mechanisms.

This article proposes the MicroStructural Hierarchy Descriptor (µSHD) as a systematic and quantitative approach to spectra and image data in microelectronics failure analysis. It discusses concrete routes for employing µSHD directly as the quantitative descriptor for supervised and unsupervised machine learning. The authors propose that µSHD tools can be used to automate and improve characterization techniques and image processing and analysis protocols.

Stress voiding is an insidious IC failure mechanism that can be difficult to identify and arrest. It is of particular concern to those who produce and test ICs with aluminum-alloy interconnects or who assess the reliability of legacy devices with long service life. This article explains how stress voids form and grow and how to determine the root cause by amassing physical evidence and ruling out other failure mechanisms. The key to differentiating stress voiding from other types of failures is recognizing that is the result of three distinct physical phenomena, stress, nucleation, and diffusion, all of which must be confirmed before attempting to make process corrections.

This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

FIB circuit edit tools and techniques have thus far kept pace with the evolution of interconnect materials in ICs and downward scaling of device dimensions. This article assesses the coming challenges for FIB circuit edit technology and the changes that will be necessary to keep FIB-based etching, milling, and deposition viable in the future.

IBM engineers have developed a holographic imaging technique, called dual-lens electron holography, that provides high spatial resolution and field of view without compromising signal-to-noise ratio. This article reviews the basic principles of the new method and provides several examples of its use. The first few examples demonstrate the junction profiling capabilities of the new method which, in one case, helps to explain why shallow junction devices are made with raised source-drain regions. In the other examples, dual-lens holography is used for strain mapping, in one case, to study strain distributions in sigma-shaped SiGe devices, and in another, to provide evidence that stress memorization occurs in dislocations in the source-drain region of nFET devices.

This article discusses the primary differences between electrostatic discharge (ESD) and electrical overstress (EOS) and the circumstances under which they occur. It also explains how to differentiate ESD from EOS during failure analysis and how to avoid common misunderstandings and mistakes.

IBM engineers recently conducted a study to better understand and control the reliability of copper pillar solder joints in 2.5-D packages. Here they describe their approach and the results they obtained. They explain how they created test samples to evaluate different solder compositions, pillar geometries, and thermal histories and assess their effect on microstructure, precipitate morphology, intermetallic layer thickness, and shear strength. They also present thermal cycling test results comparing the performance of silicon and glass interposers.