Failure analysis is becoming increasingly difficult with the emergence of 3D integrated packages due to their complex layouts, diverse materials, shrinking dimensions, and tight fits. This article demonstrates several FA techniques, including high-frequency scanning acoustic microscopy, lock-in thermography, and FIB cross-sectioning in combination with plasma ion etching or laser ablation. Detailed case studies show how the various methods can be used to analyze bonding integrity between different materials, chip-to-chip interface structures, buried interconnect defects, and through-silicon vias at either the device or package level.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

This article presents a failure analysis workflow tailored for complex ICs and device packages. The FA flow determines the root cause of failures using nondestructive analysis and advanced sample preparation techniques. The nondestructive tests typically used are X-ray radiography, scanning acoustic microscopy, time domain reflectometry, and magnetic current imaging. To gain access to interconnect failures, laser ablation is used, typically in combination with chemical etching to finish the decapsulation process. Repackaging is also part of the FA flow and is briefly discussed.

Several failure analysis case studies have been conducted over the past few years, illustrating the importance of preserving root-cause evidence by means of artifact-free decapsulation. The findings from three of those studies are presented in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also includes images that compare the results of different decapsulation methods.

The 47th International Symposium for Testing and Failure Analysis (ISTFA 2021) was held in Phoenix, Ariz., from October 31 to November 4, 2011. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, User Group meetings, and the Women in Electronics Failure Analysis (WEFA) event.

Modified Talbot X-ray interferometry provides three contrast modes simultaneously: absorption, phase, and dark field/scattering. This article describes the powerful new imaging technique and shows how it is used to characterize various types of defects in advanced semiconductor packages.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

Magnetic current imaging is a proven fault-isolation technique. Its unsurpassed sensitivity and resolution coupled with the fact that magnetic fields are unaffected by packaging and die materials make it a valuable FA tool for a wide variety of ICs and devices. This article reviews the basic measurement physics of magnetic current imaging, describes the general implementation, and presents several practical examples of its use.

This is the concluding portion of a two-part article on counterfeit ICs. The first part, published in the November 2008 issue of EDFA , discussed the rise of counterfeit ICs and some of the techniques used to identify them. Part II describes a process for device authentication, from material procurement to laboratory analysis, and provides examples of its use. It also discusses ongoing efforts to remove counterfeit ICs from the supply chain.

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.

The 38th International Symposium for Testing and Failure Analysis (ISTFA 2012) was held in Phoenix, Ariz., November 11-15, 2012. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, User’s Group meetings, and equipment exposition.

The Assembly Analytical Forum (AAF) is an organization under the auspices of the Sematech Quality Council. The AAF charter is to develop Packaging Analytical Roadmaps five to ten years into the future that are consistent with the International Technology Roadmap for semiconductors (ITRS). At ISTFA 2003, the AAF will convene with interested conference attendees to review, edit, and validate a white paper that will quantify critical gaps in the current suite of test, measurement, and characterization tools used in the semiconductor industry and provide recommendations on how to address them. The intent is to update the document biannually and review it in numerous industry venues to ensure its relevancy and utility. This article is somewhat of a preview to the Rev 0 AAF white paper.

This article describes a form of lock-in thermography that achieves 3D localization of thermally active defects in stacked die packages. In this approach, phase shifts associated with thermal propagation delay are analyzed as a function of frequency. This allows for a precise localization of defects in all three spatial dimensions and can serve as a guide for subsequent high-resolution physical analyses.

Magnetic microscopy is a defect localization technique that has several advantages. It is nondestructive, noninvasive, and contactless. In many cases, it can be used even before component depackaging. This article describes the basic setup of a magnetic current imaging (MCI) microscope and explains how it reveals 3D current paths at the package and die level. It also presents application examples showing how MCI has helped failure analysts isolate a wide range of electrical defects, including shorts, resistive opens, and full opens.

This article describes how physical attacks can be launched on different types of nonvolatile memory (NVM) cells using failure analysis tools. It explains how the bit information stored inside these devices is susceptible to read-out and fault injection attacks and defines vulnerability parameters to help quantify risks associated with different modalities of attack. It also presents an in-depth security analysis of emerging NVM technologies and discusses potential countermeasures.

This article proposes a design for a real-time Trojan detection system and explores possible solutions to the challenge of large-scale SEM image acquisition. One such solution, a deep-learning approach that generates synthetic micrographs from layout images, shows significant promise. Learning-based approaches are also used to both synthesize and classify cells. The classification outcome is matched with the design exchange format file entry to ensure the purity of the underlying IC.

Engineers at the Fraunhofer Institute for Microstructure of Materials and Systems built and are testing a scanning acoustic microscope (SAM) that operates at frequencies of up to 2 GHz. Here they describe the design of their GHz-SAM and present examples showing how it is used to detect stress induced voids, inspect wire bond interfaces, and examine through-silicon vias (TSVs) in the time-resolved mode.