Search Results for SEM imaging

This article describes an ebook titled STEM-in-SEM: Introduction to Scanning Transmission Electron Microscopy for Microelectronics Failure Analysis , intended as an introductory tutorial for those with little or no transmission imaging experience and as a source of ideas for SEM users looking to expand the imaging and diffraction capabilities of their equipment.

A detailed analysis based on FIB etching and SEM image capture was conducted on a flip-chip solder joint deep inside a tablet PC. 3D views reconstructed from SEM images show what appears to be a copper pillar with a solder cap connected to a copper trace on the substrate. The investigators believe the joint was formed by thermal compression bonding with a preapplied underfill. The analysis also revealed the presence of voids and intermetallic compounds along with signs of filler entrapment.

This article describes two innovative methods that can significantly improve the resolution of SEM imaging: scanning transmission electron microscopy in a scanning electron microscope (STEM-in-SEM) and forward-scattered electron imaging (FSEI). Both methods can be implemented in any SEM using special sample holders. No other modifications are required. Test results presented in the article show that 1 to 2 nm resolution is possible in thin sections, uncoated polysilicon gates, and photoresist.

This article proposes a design for a real-time Trojan detection system and explores possible solutions to the challenge of large-scale SEM image acquisition. One such solution, a deep-learning approach that generates synthetic micrographs from layout images, shows significant promise. Learning-based approaches are also used to both synthesize and classify cells. The classification outcome is matched with the design exchange format file entry to ensure the purity of the underlying IC.

This article discusses the challenges associated with nanoprobing advanced technology node devices and explains how to optimize SEM images for beam voltages of 100 eV or less.

Voltage contrast, a phenomenon that occurs in scanning electron microscopes, produces brightness variations in SEM images that correspond to potential variations on the test sample. Through appropriate processing, voltage contrast signals can reveal an extensive amount of information about the functionality of ICs. Voltage contrast can be used, for example, to map electrical logic levels and timing waveforms from internal nodes of the chip as it operates inside the SEM chamber. This article describes the fundamentals of voltage contrast and its applications in IC failure analysis.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

In this article, the authors evaluate micro CNC milling as an alternative to manual parallel lapping for mechanical cross-sectioning of flip-chip packaged samples. They describe both processes, and how they compare to other cross-sectioning techniques, and clearly illustrate the differences. SEM images of a manually polished sample show process-induced cracking, chipping, and delamination at the die-C4 interface. In contrast, the CNC-milled sample is artifact-free and the C4 bumps are uniformly exposed along the entire length of the cross-section.

Advanced 10 nm device delayering is a critical process for verifying and validating the circuit design layout and extracting the structures buried inside the chip. The work featured in this article takes advantage of chemically assisted focused ion beam processing with ultraviolet spectroscopy to destructively delayer integrated circuits starting from the shallow trench isolation layer, enabling high-resolution SEM imaging at each layer.

A scanning electron microscope system measures voltage contrast on device-under-test surfaces. This article addresses a limited set of applications that rely on voltage contrast (VC) measurements in SEM systems, showing how VC measurements can probe electrical activity running at speeds as high as 2 GHz on modern active integrated circuits.

The causes of failure in flip-chip packaged devices are often found at the interface between the die and package. Exposing the site of interest usually entails some form of mechanical cross-sectioning with the sample embedded in an epoxy puck. This article brings attention to some of the drawbacks with the current approach and presents a solution in the form of a redesigned puck. As test results show, the new puck significantly reduces polishing time, and when cast with a conductive epoxy, minimizes charging artifacts and image distortion during SEM analysis. It also facilitates easy sample removal for subsequent analysis.

Three case studies involving 14 nm SRAM technology show how progressive FIB cross-sectioning and top-down analysis can be supplemented with nanoprobing and TEM tomography to determine the root cause of failure. In the first case, the memory failure is traced to an abnormal gate profile. In the second case, the failure is attributed to a metal line short, and in the third case, a gate defect.

A new way to detect gate oxide defects has been developed. The method, as the article explains, is based on wet chemical etching and is particularly effective for devices with floating gates. Test samples with exposed poly-Si gates are placed in a KOH:H 2 O solution and a voltage is applied to the silicon substrate. At a certain voltage, normal gates begin to etch, while those shorted to the substrate through gate oxide defects develop an anodic oxide and thus remain unetched. This method has proven effective in assessing gate oxide integrity without direct observation of the oxide, which requires complicated deprocessing and a lot of time. It also reveals electrical characteristics of gate oxides that are difficult to identify by conventional physical analysis.

This article discusses the current state of large area integrated circuit deprocessing, the latest achievements in the development of automated deprocessing equipment, and the potential impact of advancements in gas-assisted etching, ion source alternatives, compact spectroscopy, and high-speed lasers.

This article provides a brief overview of STEM-in-SEM, discussing the pros and cons, recent advancements in detector technology, and the emergence of 4D STEM-in-SEM, a relatively new method that uses diffraction patterns recorded at different raster positions to enhance images offline in selected regions of interest.

Image enhancement has proven helpful for locating defects in ICs. This article discusses two image analysis techniques, image comparison and intensity profiling, and shows how they reveal defects that would otherwise be missed.

Experiments to assess microelectromechanical systems (MEMS) test their functionality and materials properties. These experiments provide knowledge and insight into MEMS failure modes and potential pathways to improve the lifetime of MEMS devices. This article demonstrates the use of optical microscopy and SEM analysis to determine various causes of failure in MEMS devices.

In this case study, the author describes the investigation of a defective DC-DC converter retrieved from an aircraft following the report of abnormal system behavior. Electrical testing, local probing, X-ray imaging, and cross-sectional analysis led to the discovery of cracks on several pins and in some of the solder material. The cracks were caused by different rates of thermal expansion and were remedied with the help of thermomechanical analysis, EBSD imaging, and phase map comparisons for thick and thin solder joints.

Scanning electron microscopes can be used to analyze almost anything that conducts electricity and is prone to failure, including relays, coils, inductors, capacitors, resistors, transistors, diodes, IGBTS, MOSFETS, and hybrid circuits. As the author of the article explains, SEMs are one of the most versatile tools for failure analysis if used to the full extent of their capabilities. Their operating modes include emissive imaging, backscattering, voltage contrast, EBIC or specimen current, and conductivity resistive mapping. The author describes each operating mode and presents examples of the various ways they can be used.

This article presents a method for determining the integrity of solder joints made from mixed and lead-free solders. It discusses the procedures involved in sample preparation and testing and explains how to interpret the results, particularly the effect intermetallic formation, cracking, and voiding.