This article explains how the addition of FIB tunable circuits in critical paths on ICs can alleviate some of the challenges encountered during the implementation of mixed-signal ASICs. It walks readers through the implementation of a particular digital ASIC, explaining where and how FIB tunable circuits were used to overcome difficulties, resolve problems, and realize a fully functional chip that met all system specifications on the first pass of the design.

Flip chip mounted devices are difficult debug using conventional FIB tools because their internal circuitry is not easily accessible. New flip chip focused ion beam (FC FIB) systems overcome this limitation, however, making it possible to access circuits from the backside through the bulk silicon. In this article, the authors explain how they used the new system to gain access to signal lines for backside waveform acquisition. They also describe some of the procedures they developed to repair and modify flip chip circuits from the backside and prepare cross-section samples from the backside for failure analysis and characterization.

Technologies relatively new to failure analysis, like time-correlated photon counting, electro-optical probing, antireflective (AR) coating, Schlieren microscopy, and superconducting quantum interference (SQUID) devices are being leveraged to create faster, more powerful tools to meet increasingly difficult challenges in failure analysis. This article reviews recent advances and research in fault isolation and circuit repair.

Metrology targets are an essential tool for evaluating the performance of imaging systems and maintaining their accuracy over time. Ideally, the pattern on the target is simple enough that the expected image is intuitive or, at least, easily simulated. Although many such targets exist for frontside imaging, until recently, few if any could be found for backside applications. In this article, the first of a two-part series, the authors explain how they addressed this gap by converting a readily available frontside target for backside use. The conversion process is described step by step in enough detail that it can be replicated in order to convert other frontside targets. Due to the success of the converted target, an unmounted, backside-specific version has subsequently been developed, the availability of which not only eliminates one of the more difficult steps in the original conversion process, but also provides additional benefits. Using one of these newer targets, the authors evaluated a backside imaging system consisting of a laser scanning microscope (LSM) and a solid immersion lens (SIL). The results are presented here along with the criteria used for the evaluation. Other applications of the new metrology target as well as its limitations are discussed in the May 2015 issue of EDFA .

The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.

Broad ion beam delayering is a versatile technique for whole-chip failure analysis. The large area of uniformity coupled with the ability to precisely stop at the layer of interest facilitates repeatable, rapid defect detection anywhere on the chip.

This ISTFA panel discussed opportunities and challenges related to failure analysis facilities shared by multiple companies. The factors to consider and some examples of what’s being done were presented and discussed by the panel members.

FIB circuit edit tools and techniques have thus far kept pace with the evolution of interconnect materials in ICs and downward scaling of device dimensions. This article assesses the coming challenges for FIB circuit edit technology and the changes that will be necessary to keep FIB-based etching, milling, and deposition viable in the future.

This article provides an introduction to focused ion beam (FIB) circuit editing, covering the basic process along with best practices and procedures.

This article discusses the generation of heat that occurs in ICs during failure analysis and examines the effectiveness of various die cooling techniques including heat spreading films, spray cooling, and liquid and air jet impingement.

Picosecond imaging circuit analysis (PICA) is an advanced diagnostic technique that measures device switching activity on CMOS ICs through the backside of the die. Due to its relatively large field of view, it can quickly locate defects among large numbers of candidates. In this case study, the authors explain how they used PICA to identify a particular I/O circuit defect on the IBM System/390 G5 microprocessor. They also explain how they verified the diagnostic result using circuit simulations.

This article examines current research into the building blocks of the nanoscale system and the techniques used to synthesize them. Also explored are some proposed ideas and the challenges associated with integrating these building blocks into molecular nanosystems such as chemically assembled electronic nanocomputers (CAENs).

Circuit boards are vulnerable to a wide range of ill-intentioned modifications done to gain access to information or malevolently influence control. This article describes the various ways attacks on circuit board can occur and presents examples showing how such attacks might look. It also provides general guidelines for protecting circuit-board design integrity.

This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

This article discusses the causes and effects of parasitic ringing in the gate drive circuit of dc-to-dc converters. It also presents experimental results validating a possible solution.

This article presents a method for determining the integrity of solder joints made from mixed and lead-free solders. It discusses the procedures involved in sample preparation and testing and explains how to interpret the results, particularly the effect intermetallic formation, cracking, and voiding.

This article demonstrates the strengths and limitations of electrical testing for locating defects that contribute to contact failures in DRAMs. It presents three case studies, the first of which involves a write problem to a pair of cells that share an open bitline contact. The second case, a read problem between the primary and secondary sense amplifiers, serves as an example of how failure bitmaps and electrical characterization work together to detect and locate defects. The third case is a decoder problem that required additional testing and internal probing in order to determine the location of the defect.