TEM specimens prepared using a Ga FIB are susceptible to artifacts, such as surface amorphization and ion-implanted layers, that can be problematic in advanced technology nodes, particularly for FinFETs. As this article shows, however, post-FIB cleaning via concentrated argon ion milling makes for a fast and effective specimen preparation process for FinFET devices controlled to a thickness of less than 20 nm. Although the results presented here are based on 14 nm node FinFETs, the method is also applicable to the 10 and 7 nm FinFET technologies currently in production.

This article discusses the practice of FIB-based in situ lift-out, a sample preparation method that has proven particularly useful for failure analysis. It explains how samples are now being made for a wide range of TEM techniques, including holography, tomography, high-angle annular dark-field scanning, and electron energy-loss spectroscopy. In most cases, achieving optimal quality requires the use of alternate FIB milling angles, as in plan-view, sideways, and backside milling, all of which are discussed.

FIB milling is difficult if not impossible with III-V compound semiconductors and certain interconnect metals because the materials do not react well with the gallium used in most FIB systems. This article discusses the nature of the problem and explains how cryogenic FIB-SEM techniques provide a solution. It describes the basic setup of a FIB-SEM system and provides examples of its use on InN nanocrystals, GaN films, and copper-containing multilayer photovoltaic materials.

Shortcuts in failure analysis are sometimes to save time or money or because equipment or expertise is unavailable. This article presents simple but effective solutions in four areas, including deprocessing, FIB milling, microcleaving, and TEM sample preparation, that may help analysts work through or around such situations.

The complexity of sample preparation and deprocessing has risen exponentially with the emergence of 2.5-D and 3D packages. This article provides answers and insights on how to deal with the challenges of increasingly complex semiconductor packages. After identifying pressing issues and potential bottlenecks with state-of-the-art FA flows, the authors present two case studies demonstrating the capabilities of electro-optical terahertz pulse reflectometry (EOTPR), plasma FIB milling, and 3D X-ray imaging. The FA results confirm the potential of all three techniques and indicate that a fully nondestructive integration flow for 3D packages may be achievable with further development and optimization.

Ex-situ lift out (EXLO) techniques rely on van der Waals forces to transfer FIB milled specimens to various types of carriers using a glass probe micromanipulator. This article describes some of the latest EXLO techniques for site specific scanning transmission electron microscopy, including the use slotted half-grids and vacuum-assisted lift out for plan-view analysis.

High-frequency devices such as monolithic microwave ICs (MMICs) are used in telecommunication devices as well as in satellites for earth imaging and radar applications. This article discusses the use of focused ion beam (FIB) cross sectioning and sample decoration techniques for analyzing MMICs and III-V materials.

The sixth FIB-SEM workshop was held March 1, 2013, in Cambridge, Mass. This article provides a summary of the event along with highlights from the 18 paper presentations.

Thin film anomalies cause many device failures but they are often difficult to see. In this article, the authors explain how they found and identified an 8 to 10 nm film of tantalum causing pin shorts in a majority of ASIC modules from a particular lot. Initial attempts to delayer some of the failed modules resulted in the loss of the failure signal. It was then decided to use a focused ion beam to selectively mill through the interlayer dielectric. During milling, a secondary electron image revealed anomalous material between the fingers of a power transistor, which was subsequently identified as tantalum. Such defects, as the authors explain, are common in damascene processes when materials are not properly removed during etching.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.

FIB circuit edit tools and techniques have thus far kept pace with the evolution of interconnect materials in ICs and downward scaling of device dimensions. This article assesses the coming challenges for FIB circuit edit technology and the changes that will be necessary to keep FIB-based etching, milling, and deposition viable in the future.

Failure analysis is becoming increasingly difficult with the emergence of 3D integrated packages due to their complex layouts, diverse materials, shrinking dimensions, and tight fits. This article demonstrates several FA techniques, including high-frequency scanning acoustic microscopy, lock-in thermography, and FIB cross-sectioning in combination with plasma ion etching or laser ablation. Detailed case studies show how the various methods can be used to analyze bonding integrity between different materials, chip-to-chip interface structures, buried interconnect defects, and through-silicon vias at either the device or package level.

Designing circuit edits at the contact level offers tremendous advantages in reliability and yield success over similar edits designed in the metal stack. To that end, a full-thickness backside circuit edit strategy has been developed that eliminates part thinning and promotes the implementation of all edits at the contact level to avoid milling into the metal layers. This article describes the FIB-based circuit edit process and presents several case studies demonstrating its use on 65 nm technology devices.

Atomic force microscopy has been a consistent factor in the advancements of the past decade in IC nanoprobing and failure analysis. Over that time, many new atomic force measurement techniques have been adopted by the IC analysis community, including scanning conductance, scanning capacitance, pulsed current-voltage, and capacitance-voltage spectroscopy. More recently, two new techniques have emerged: diamond probe milling and electrostatic force microscopy (EFM). As the authors of the article explain, diamond probe milling using an atomic force microscope is a promising new method for in situ, localized, precision delayering of ICs, while active EFM is a nondestructive alternative to EBAC microscopy for localization of opens in IC analysis.

Flip chip mounted devices are difficult debug using conventional FIB tools because their internal circuitry is not easily accessible. New flip chip focused ion beam (FC FIB) systems overcome this limitation, however, making it possible to access circuits from the backside through the bulk silicon. In this article, the authors explain how they used the new system to gain access to signal lines for backside waveform acquisition. They also describe some of the procedures they developed to repair and modify flip chip circuits from the backside and prepare cross-section samples from the backside for failure analysis and characterization.

A recent trend in semiconductor failure analysis involves combining the use of different tools and techniques in order to acquire more accurate data at a faster rate. This article describes a new workflow that combines FIB, GIS, and nanoprobing, all performed at the same FIB tilt position. It also provides two examples in which the workflow is used.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

Plasma focused ion beam (PFIB) systems can generate ion beams with much higher current and are therefore able to remove larger volumes of material at much faster rates while still maintaining precise control of the beam and its milling action. This article explains how the improved performance of PFIB is leading to new applications in delayering, deprocessing, and site-specific failure analysis.

The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.