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Journal Articles
EDFA Technical Articles (1999) 1 (2): 13–22.
Published: 01 May 1999
...J.M. Soden; C.L. Henderson; E.I. Cole, Jr. Sandia National Laboratories manufactures 0.5 µm CMOS ICs using local oxidation of silicon (LOCOS) and shallow trench isolation (STI) technologies. A program based on burn-in and life tests is being used to qualify the process for military and space...
Journal Articles
EDFA Technical Articles (2005) 7 (3): 14–21.
Published: 01 August 2005
... LEOSLC light emission logic state off-state leakage current power distribution noise httpsdoi.org/10.31399/asm.edfa.2005-3.p014 EDFAAO (2005) 3:14-21 Off-State Light Emission 1537-0755/$19.00 ©ASM International® CMOS IC Diagnostics Using the Light Emission from Off-State Leakage Currents (LEOSLC...
Journal Articles
EDFA Technical Articles (2000) 2 (3): 20–25.
Published: 01 August 2000
...Wai Mun Yee; Mario Paniccia; Travis Eiles; Valluri Rao Laser voltage probing (LVP), an IR-based technique, facilitates through-silicon signal waveform acquisition and high frequency timing measurements from active p-n junctions on CMOS ICs. The ICs can be in flip-chip as well as wire-bond packages...
Journal Articles
EDFA Technical Articles (2002) 4 (3): 5–9.
Published: 01 August 2002
...Anne Gattiker; Jerry Soden; Chuck Hawkins CMOS IC failure mechanisms are of three general types: bridge defects, open circuit defects, and parametric related failures. This article summarizes bridge and open-circuit defect properties and provides references for further self-study. Bridge defects...
Journal Articles
EDFA Technical Articles (2006) 8 (3): 12–17.
Published: 01 August 2006
...Victor Champac; Roberto Gomez; Chuck Hawkins This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute...
Journal Articles
EDFA Technical Articles (2022) 24 (1): 3–10.
Published: 01 February 2022
... procedure and demonstrate its use on complex semiconductor pad stacks. They also present experimental results that shed new light on the relationship between probe tip contact force and crack probability in thin, brittle layers typical of BEOL layer stacks in CMOS ICs. Engineers at Infineon Technologies...
Journal Articles
EDFA Technical Articles (2002) 4 (1): 12–16.
Published: 01 February 2002
...Peilin Song; Moyra McManus; Franco Motika; Steven Steen; Dan Knebel; Julie Lee Picosecond imaging circuit analysis (PICA) is an advanced diagnostic technique that measures device switching activity on CMOS ICs through the backside of the die. Due to its relatively large field of view, it can...
Journal Articles
EDFA Technical Articles (2006) 8 (2): 14–20.
Published: 01 May 2006
...Magali Lamy; Marc de la Bardonnie; Frederic Lorut; Ryan Ross; Christophe Wyon; Laurens F. Tz. Kwakman This article assesses the capabilities of failure analysis techniques in the context of 65 nm CMOS ICs. It demonstrates the use of OBIRCH, voltage contrast, Seebeck effect imaging, SEM and TEM...
Journal Articles
EDFA Technical Articles (2006) 8 (4): 16–24.
Published: 01 November 2006
... electromagnetic susceptibility. It explains how to determine susceptibility based on transient pulse testing and presents and interprets the test results of three automotive ICs. Copyright © ASM International® 2006 2006 ASM International CMOS ICs failure signatures transient electromagnetic...
Journal Articles
EDFA Technical Articles (2003) 5 (2): 5–9.
Published: 01 May 2003
... International Nanoelectronics Failure Analysis Dave Vallett, IBM Microelectronics Division dvallett@us.ibm.com Introduction In the fourth quarter 2002 issue, we examined the future of failure analysis on so-called microelectronic devices in other words CMOS ICs and derivatives described by the SIA Roadmap...
Journal Articles
EDFA Technical Articles (1999) 1 (3): 1–28.
Published: 01 August 1999
... IC Technology and Testing Issues Roadmaps . . . 6 Useful URLs 18 Case Alan Righter Analog Devices Inc. Histories . . 19 SEM for General Purpose FA 21 Diagnosis of CMOS ICs with digital circuitry is aided by the relative ease of test equipment Training Calendar 29 capability to provide logic high...
Journal Articles
EDFA Technical Articles (2001) 3 (1): 20–23.
Published: 01 February 2001
... for resolving CMOS latch-up. Another major reliability problem that faced CMOS technology was the extreme ESD susceptibility of the initial CMOS ICs at the input/output pins3. For 15 years, nMOS technologies used ESD protection devices that harmlessly dissipated the energy of the ESD event. However, when...
Journal Articles
EDFA Technical Articles (2008) 10 (1): 46–47.
Published: 01 February 2008
... the CMOS IC with new materials and new device structures. More than Moore says the important point is not faster, better, and cheaper ICs per se but faster, better, and cheaper end products. This can be accomplished through a much higher level of post-IC fab integration (e.g., system on a chip or system...
Journal Articles
EDFA Technical Articles (2001) 3 (4): 29–35.
Published: 01 November 2001
... techniques that normally require FIB and microprobing. CMOS Devices The previous experiments were performed to validate the SCOBIC to equivalent OBIC results. SCOBIC could image all the junctions in an IC as compared to OBIC that only images junctions directly connected to the instrumentation. For SCOBIC...
Journal Articles
EDFA Technical Articles (2004) 6 (3): 13–18.
Published: 01 August 2004
...-5.4. 4. J. Segura, A. Keshavarzi, J. Soden, and C. Hawkins: Parametric Failures in CMOS ICs A Defect-Based Analysis, Int. Test Conf. (ITC), Oct. 2002, pp. 90-99. 5. A. Righter, C. Hawkins, J. Soden, and P. Maxwell: CMOS IC Reliability Indicators and Burn-In Economics, Int. Test Conf. (ITC), Nov...
Journal Articles
EDFA Technical Articles (2000) 2 (4): 25–30.
Published: 01 November 2000
... the failure in the laboratory, it would require more time and effort. The need for timely failure isolation techniques in product engineering and yield enhancement is tenfold because lengthy analyses can be costly4. IDDQ Scan IDDQ testing is a powerful method for defect localization CMOS ICs because...
Journal Articles
EDFA Technical Articles (2006) 8 (3): 18–24.
Published: 01 August 2006
... CMOS IC Stuck-Open-Fault Electrical Effects and Design Considerations, J.M. Soden, R.K. Treece, M.R. Taylor, and C.F. Hawkins ATPG for Ultra-Large Structured Designs, J. Waicukauski, P. Shupe, D. Giramma, and A. Matin Sequencer-per-Pin Test System Architecture, B. West and T. Napier A Language...
Journal Articles
EDFA Technical Articles (2002) 4 (4): 11–16.
Published: 01 November 2002
... research specialty is the electronic properties of defective CMOS ICs, which is the basis for an upcoming co-authored book titled CMOS Electronics: How it Works, How it Fails. He is Past General and Program Chair of International Test Conference, and he is currently the Editor of this magazine and a member...
Journal Articles
EDFA Technical Articles (2004) 6 (3): 20–30.
Published: 01 August 2004
.... In this article, they describe the work they performed along with the findings and provide practical guidelines on how to minimize latchup regardless of the IC technology involved. Copyright © ASM International® 2004 2004 ASM International emission microscopy I/O circuits latchup n -well substrate...
Journal Articles
EDFA Technical Articles (2004) 6 (1): 13–21.
Published: 01 February 2004
... Designs, VLSI Tech. Symp. Digest, 1997, pp. 69-70. 4. A. Keshavarzi, S. Narenda, S. Borkar, C. Hawkins, K. Roy, and V. Dey: Technology Scaling Behavior of Optimum Reverse Body Bias for Leakage Power Reduction in CMOS IC s, Proc. ISLPED, 1999, pp. 252-54. 5. Y. Taur and T. Ning: Fundamentals of Modern...