This editorial discusses the emergence of chiplets and its potential impact on IC design, fabrication, and failure analysis.

Chip-level 3D integration, where chips are thinned, stacked, and vertically interconnected using TSVs and microbumps, brings as many challenges as it does improvements, particularly in the area of failure analysis. This article assesses the capabilities of various FA techniques in light of the challenges posed by 3D integration and identifies current shortcomings and future needs.

This article describes a form of lock-in thermography that achieves 3D localization of thermally active defects in stacked die packages. In this approach, phase shifts associated with thermal propagation delay are analyzed as a function of frequency. This allows for a precise localization of defects in all three spatial dimensions and can serve as a guide for subsequent high-resolution physical analyses.

This column is part of a series of reports on the findings to date of the EDFAS Failure Analysis Roadmap Councils. The Failure Analysis Future Roadmap Council (FAFRC) is concerned with identifying the longer term needs of the FA community. This article discusses analysis challenges associated with the growing number of elements being incorporated into integrated circuit fabrication. It includes tables summarizing top challenges in front end and package analysis.

The Package Innovation Roadmap Council (PIRC) was established as part of the Failure Analysis Technology Roadmap activity at the direction of the EDFAS Board. This column provides an overview of a technical paper by the PIRC that highlights recent innovations, technology gaps, and future development trends in package fault isolation and failure analysis. The paper focuses on three main categories: 1) Artificial intelligence (AI) applications, 2) Sample handling, and 3) FA tool robustness.

This article discusses the basic procedures involved in atom probe tomography (APT) and demonstrates its use on complex material stacks. Although still a relatively new technique, APT has moved to the forefront of semiconductor failure analysis because it can provide 3D chemical composition of a wide range of materials on a near-atomic scale.

This column provides an update on the latest developments in 3D IC technology and outlines the work that still remains before the promises of full 3D integration can be realized.

The 45th International Symposium for Testing and Failure Analysis (ISTFA 2019) was held in Portland, Oregon, November 10-14, 2019. This article gives a brief summary of the highlights and identifies key contributors to the event. It also includes highlights of panel discussions from the inaugural meeting of Women in Electronics Failure Analysis (WEFA) and the panel discussion "What Does Artificial Intelligence Mean to Failure Analysis Engineers?" The article concludes with a brief recap of each of the four User Group meetings that took place during the conference: Sample Prep, System on Package, FIB/Circuit Edit, and Nanoprobing.

This column explains that silicon interposers, considered an interim solution to full 3D integration, may turn out to be more than a stepping stone along the path toward 3D ICs.

Failure analysis labs are fairly well equipped for dealing with shorts and leakages in stacked-die packages, but are at a disadvantage when it comes to opens, particularly those at the die or die interconnect level. This article presents a new FA technique that has the potential to make up for this shortcoming. The new method, called space domain reflectometry (SDR), is based on radio-frequency magnetic current imaging, and as the authors show, is capable of accurately locating a dead open in a double-stacked BGA package, even when the full stack is encapsulated in molding compound.

The complexity of sample preparation and deprocessing has risen exponentially with the emergence of 2.5-D and 3D packages. This article provides answers and insights on how to deal with the challenges of increasingly complex semiconductor packages. After identifying pressing issues and potential bottlenecks with state-of-the-art FA flows, the authors present two case studies demonstrating the capabilities of electro-optical terahertz pulse reflectometry (EOTPR), plasma FIB milling, and 3D X-ray imaging. The FA results confirm the potential of all three techniques and indicate that a fully nondestructive integration flow for 3D packages may be achievable with further development and optimization.

Failure analysis is becoming increasingly difficult with the emergence of 3D integrated packages due to their complex layouts, diverse materials, shrinking dimensions, and tight fits. This article demonstrates several FA techniques, including high-frequency scanning acoustic microscopy, lock-in thermography, and FIB cross-sectioning in combination with plasma ion etching or laser ablation. Detailed case studies show how the various methods can be used to analyze bonding integrity between different materials, chip-to-chip interface structures, buried interconnect defects, and through-silicon vias at either the device or package level.

The pace of development for 2.5-D packaging solutions appears to be accelerating as the timeline for the adoption of 3D through-silicon via (TSV) technology continues to slide. This column discusses the latest advancements in 2.5-D or interposer packaging technology and the growing number of applications.

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.

This column provides commentary about the 2020 EDFAS Virtual Workshop. Highlights from the three days of online sessions include a keynote address on the history of MEMS, a panel discussion on 3D packaging technologies, and nearly 60 technical papers and posters. Workshop attendees also had the opportunity to walk through a virtual Expo Hall and learn about new analytical tools and techniques and interact with equipment vendors.

This article assesses the progress that has been made in the development and implementation of through-silicon via (TSV) technology, the work yet to be done, and the challenges associated with potential failure mechanisms.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

The semiconductor industry has followed Moore’s law in the last four decades. However, transistor performance improvement will be limited, and designers will not see doubling of frequency every two years. The need for increased performance and further miniaturization has driven the development of advanced packaging solutions, such as fan-in wafer-level chip-scale packaging, fan-out wafer-level packaging, wire-bonded stacked dice, and package-on-package. These technologies are used in mass production and provide significant benefits in form factor but may not give the desired improvement in die-to-die bandwidth. Recently, 3-D integrated circuits (ICs) that employ vertical through-silicon vias (TSVs) for connecting each die have been proposed. It is an alternative solution to existing package-on-package and system-in-package processes. This column addresses some of the challenges in implementing new TSV techniques.

This article discusses the concept of a virtual known good device (VKGD) and how it used in the development of advanced 3D packaging. It explains that a VKGD is essentially an electromagnetic model of an IC package, including bumps, interposers, and through-silicon vias. These models, used in conjunction with reflectometry data, help engineers isolate faults in the early stages of IC package development, greatly reducing cycle times.

This article provides a recap and summaries of the EDFAS Virtual User Group Workshop held in January 2021. The summaries cover key participants, presentation topics, and discussion highlights from the Focused Ion Beam, Sample Preparation, Contactless Probing and Nanoprobing, and System on Package virtual group meetings.