This article introduces silicon photonics, describes what is needed for photonics failure analysis, and shows examples of analysis results for failures in modern silicon photonics circuits.

The 1997 National Technology Roadmap for Semiconductors (NTRS) and the 1999 International Technology Roadmap for Semiconductors (ITRS) include chapters outlining metrology needs for the silicon semiconductor industry during the next five years and beyond1. The grand challenges include affordable scaling, new materials and structures, and yield and reliability. Although additional requirements within these categories are detailed, it is often difficult for the analytical specialist or metrology equipment vendor to translate these grand challenges into detailed and meaningful roadmaps for success in analytical applications or instrument development. The path-to-impact of a single metrology activity is not always clear.

A new preferential etch for (100) and (111) oriented, p- and n-type silicon has been developed. This article describes the basic chemistry of the etching process and provides examples of how it defines critical features such as oxidation-induced stacking faults, dislocations, swirl, and striations with minimum surface roughness and pitting. A relatively slow etch rate of around 1 μm/min at room temperature provides etch good control and a long shelf life allows the solution to be stored in large quantities.