This article provides a systematic overview of knowledge-based and machine-learning AI methods and their potential for use in automated testing, defect identification, fault prediction, root cause analysis, and equipment scheduling. It also discusses the role of decision-making rules, image annotations, and ontologies in automated workflows, data sharing, and interoperability.

The failure of a white LED backlight module in a portable computer illustrates the challenges that component and system suppliers must overcome in order to determine root-cause failure mechanisms and take corrective actions that address the problem.

Several failure analysis case studies have been conducted over the past few years, illustrating the importance of preserving root-cause evidence by means of artifact-free decapsulation. The findings from three of those studies are presented in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also includes images that compare the results of different decapsulation methods.

This columnn explores the idea that insights into the root cause of increasingly complex failures may be hidden in unanswered questions from past analyses, indicating that there might be more value in previous files than once thought.

This column presents a detailed flowchart for failure analysis.

Automotive electronics are exposed to mechanical shock and vibration, thermal cycling, chemical attack, current and voltage spikes, electromagnetic interference, and other hazards. Early life failures, which are not uncommon, can be difficult to diagnose due to the many contributing factors. This article provides an overview of automotive electronic failures and presents guidelines for determining the root cause.

This is the second article in a two-part series investigating solder connection failures associated with BGA packages. Part I, in the February 2017 issue of EDFA, examines various cases of open and short circuit failures, discusses the formation of voids, and explains how to reveal important clues by grinding away the BGA package. Part II continues the analysis of voids and focuses in on failures due to circuit board faults. In such cases, the board is ground away from the backside, stopping just short of the first inner copper layer. The alignment of the two uppermost copper layers, the integrity of microvias, and other potential problems are then examined using polarized light which readily passes through the remaining resin and fibers. As the examples in the article show, this approach can reveal a wide range of manufacturing defects in PCBs.

This article is the first in a two-part series analyzing solder connection failures between BGA packages and PCB assemblies. Part I examines failures attributed to oxygen intrusion during reflow, underetched solder resist, and solder paste printing problems. In the latter case, X-ray inspection revealed no abnormalities other than a variation in ball size. To get to the root cause, the corpus of the BGA was progressively ground away, leaving only the balls and an unobstructed view of the PCB surface. A description of the process, supported by detailed images, is included in the article. In Part II, scheduled for the May 2017 issue of EDFA, the author delves deeper into the analysis of voids and presents an alternate FA approach that involves grinding away much of the PCB.

This article explains how safety investigators with the French Bureau of Enquiry and Analysis for Civil Aviation Safety (BEA) used chip-level recovery procedures to retrieve recorded flight data that helped them piece together the events that led up to helicopter accident that recently occurred in French Guyana. The recovered data along with eyewitness accounts and findings from an assortment of tests indicated that the failure of a capacitor filtering the output of a current generator inside the engine fuel automatic regulation system obliged the pilot to control fuel regulation manually. Although other factors were involved, as the article explains, the capacitor failure played a major role in the crash.

Four panel members participated in the ISTFA 2014 Panel Discussion on the importance of correctly determining the cause of failure in electronic devices and systems designated for use in space, downhole drilling, and other such applications. Reliability of these components is critical because they cannot be easily replaced and malfunctions can be catastrophic. The panelists presented several methods for analyzing failures in integrated electrical systems and identifying the root cause.

The tools of the trade in semiconductor failure analysis have advanced rapidly over the past few decades, bringing major improvements in imaging, deprocessing, and materials analysis. In contrast to the progress made in physical FA, little attention has been given to the failure analysis process itself. This article shows through case studies how simple oversights and misunderstandings can lead to costly mistakes. It also defines basic FA concepts and presents a failure analysis sequence, describing each step along with common pitfalls and best practices.

This column suggests that developing 3D structural models as tools for observing and exploring failures in the virtual domain could prove instrumental in avoiding failure without committing hardware. Likewise, instead of building hardware to systematically evaluate failures in the presence of random effects, virtualization through a 3D model could provide a completely user-defined environment for conducting controlled experiments. In such a virtual environment, systematic and random behaviors can be introduced and parsed to provide greater clarity in the search for root causes of failure.

This article discusses the primary differences between electrostatic discharge (ESD) and electrical overstress (EOS) and the circumstances under which they occur. It also explains how to differentiate ESD from EOS during failure analysis and how to avoid common misunderstandings and mistakes.

Root-cause analysis and FA work hand-in-hand to identify the source of a problem, gather relevant data, and resolve the issue. However, even experienced professionals can succeed in FA while failing in the outcome. This article explains how to avoid common traps, dead ends, and faulty thought processes in the search for root causes.

This article presents a case study involving flash memory bit failures characterized by threshold voltage changes due to positive gate disturb stress. An inconsistency in failing bit behavior, which was found to be dependent on the test mode, was explored to provide an electrical explanation for the failure. The underlying defect was isolated and subsequently identified by physical analysis.

Diagnostic failure analysis tools provide essential information about where a defect is located and what materials are present, but that information must be combined with other data to establish cause and corrective action. Mistakes made at this stage of the investigation can be extremely costly. This article identifies some of the pitfalls and traps that failure analysts can fall into and explains how to avoid them. It provides three examples of misdiagnosed failures and helps readers to see what led analysts astray.

This article presents a failure analysis workflow tailored for complex ICs and device packages. The FA flow determines the root cause of failures using nondestructive analysis and advanced sample preparation techniques. The nondestructive tests typically used are X-ray radiography, scanning acoustic microscopy, time domain reflectometry, and magnetic current imaging. To gain access to interconnect failures, laser ablation is used, typically in combination with chemical etching to finish the decapsulation process. Repackaging is also part of the FA flow and is briefly discussed.

Scan-logic diagnosis is used in industry for three main purposes: root-cause analysis, improving manufacturing processes, and improving designs. This article reviews the principles of scan-logic diagnosis and its applications in each of the three areas. It also discusses ongoing challenges and emerging approaches.

This is a case study of an illumination-sensitive failure. Due to the unavailability of a scanning optical microscope, fault isolation was performed using a different approach based on available equipment. Through a combination of emission microscopy, FIB isolation, mechanical probing, and in-depth circuit analysis, the root cause and failure mechanism were determined.

Stress voiding is an insidious IC failure mechanism that can be difficult to identify and arrest. It is of particular concern to those who produce and test ICs with aluminum-alloy interconnects or who assess the reliability of legacy devices with long service life. This article explains how stress voids form and grow and how to determine the root cause by amassing physical evidence and ruling out other failure mechanisms. The key to differentiating stress voiding from other types of failures is recognizing that is the result of three distinct physical phenomena, stress, nucleation, and diffusion, all of which must be confirmed before attempting to make process corrections.