This article discusses the failure analysis challenges associated with large overmolded 2.5D packages and explains how laser decapsulation followed by microwave-induced plasma (MIP) spot etching removes overmold while keeping everything else intact. It also describes a defect isolation procedure in which the sample is analyzed in a large chamber environmental SEM with its ball grid array directly wired to an EBAC amplifier.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

A detailed analysis based on FIB etching and SEM image capture was conducted on a flip-chip solder joint deep inside a tablet PC. 3D views reconstructed from SEM images show what appears to be a copper pillar with a solder cap connected to a copper trace on the substrate. The investigators believe the joint was formed by thermal compression bonding with a preapplied underfill. The analysis also revealed the presence of voids and intermetallic compounds along with signs of filler entrapment.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.

The combination of microcleaving and precision broad ion beam techniques allows failure analysts to prepare site-specific specimens for SEM analysis with 0.5 μm accuracy. Microcleaving, as the article explains, uses the cleaving characteristics inherent in single-crystal semiconductor substrates. Because the substrate has significantly more mass than the process layers, it dictates the overall cross-section quality and precision of the sample. The cleave loses no material, preserves the integrity of the designated area, and enables analysis of both sides of the cross-section. When the cleave is off-set due to a buried target or when debris lies on the surface of the cross-section, ion beam etching and coating are used to fine tune the cleave location and remove debris prior to SEM analysis.

Unit level traceability (ULT) is a powerful tool that allows complete die histories to be accessed in the course of testing and analysis. It is especially useful for identifying the likely causes of microprocessor failures and in cases where failure analysis resources are limited. In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus control. Another failure, observed after burn-in, was traced to the presence of residual titanium left after metal etch.

A new preferential etch for (100) and (111) oriented, p- and n-type silicon has been developed. This article describes the basic chemistry of the etching process and provides examples of how it defines critical features such as oxidation-induced stacking faults, dislocations, swirl, and striations with minimum surface roughness and pitting. A relatively slow etch rate of around 1 μm/min at room temperature provides etch good control and a long shelf life allows the solution to be stored in large quantities.

A new way to detect gate oxide defects has been developed. The method, as the article explains, is based on wet chemical etching and is particularly effective for devices with floating gates. Test samples with exposed poly-Si gates are placed in a KOH:H 2 O solution and a voltage is applied to the silicon substrate. At a certain voltage, normal gates begin to etch, while those shorted to the substrate through gate oxide defects develop an anodic oxide and thus remain unetched. This method has proven effective in assessing gate oxide integrity without direct observation of the oxide, which requires complicated deprocessing and a lot of time. It also reveals electrical characteristics of gate oxides that are difficult to identify by conventional physical analysis.