Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

In this article, the authors evaluate micro CNC milling as an alternative to manual parallel lapping for mechanical cross-sectioning of flip-chip packaged samples. They describe both processes, and how they compare to other cross-sectioning techniques, and clearly illustrate the differences. SEM images of a manually polished sample show process-induced cracking, chipping, and delamination at the die-C4 interface. In contrast, the CNC-milled sample is artifact-free and the C4 bumps are uniformly exposed along the entire length of the cross-section.

An optically polished silicon surface with controlled sample thickness is the key to successful backside imaging. Achieving that manually can be very difficult in cases where ICs are encapsulated in packaging materials. This article describes the challenges involved with traditional (manual) backside silicon sample preparation techniques and the improvements obtainable with automation.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.

This article describes an automated sample preparation process for SEM and TEM analysis based on submicron polishing. The method uses robotics, image processing, and a polishing wheel under computer control for a fully automated recipe-driven process that creates exact cross-sections with 0.1 μm accuracy.

This article describes a sample preparation technique by which specific areas on integrated circuits can be manually polished to TEM transparency. The technique, called tripod polishing or the wedge method, produces cross-section samples within a few hours that require little or no additional thinning for TEM analysis. The method can also be used to prepare plan view TEM samples as well as samples for SEM analysis and light microscopy.