Lock-in thermography (LIT) is a widely used nondestructive tool for detecting the failure location in integrated circuits. The image pattern recognition algorithm for detecting LIT hotspots benefits image processing and can be leveraged to automate failure analysis processes.

Four-dimensional scanning transmission electron microscopy (4D-STEM) is a spatially resolved electron diffraction technique that records the electron scattering distribution at each sampling point. 4D-STEM provides researchers with information that can be analyzed in a multitude of ways to characterize a sample’s structure, including imaging, strain measurement, and defect analysis. This article introduces the basics of the technique and some areas of application with an emphasis on semiconductor materials.

This article introduces silicon photonics, describes what is needed for photonics failure analysis, and shows examples of analysis results for failures in modern silicon photonics circuits.

The Electronic Device Failure Analysis Society established the Die-Level Post-Isolation Domain Council to provide an overview of the upcoming challenges in this area and guide technique developments for next-generation analytical tools. This column summarizes the findings of the council in the areas of sample preparation, microscopy, nanoprobing, circuit editing, and scanning probe microscopy. It is a preview of the full roadmap document, which is in preparation to be released to the EDFAS community.

Broad ion beam delayering is a versatile technique for whole-chip failure analysis. The large area of uniformity coupled with the ability to precisely stop at the layer of interest facilitates repeatable, rapid defect detection anywhere on the chip.

This article provides an introduction to focused ion beam (FIB) circuit editing, covering the basic process along with best practices and procedures.

This article provides a systematic overview of knowledge-based and machine-learning AI methods and their potential for use in automated testing, defect identification, fault prediction, root cause analysis, and equipment scheduling. It also discusses the role of decision-making rules, image annotations, and ontologies in automated workflows, data sharing, and interoperability.

The Package Innovation Roadmap Council (PIRC) was established as part of the Failure Analysis Technology Roadmap activity at the direction of the EDFAS Board. This column provides an overview of a technical paper by the PIRC that highlights recent innovations, technology gaps, and future development trends in package fault isolation and failure analysis. The paper focuses on three main categories: 1) Artificial intelligence (AI) applications, 2) Sample handling, and 3) FA tool robustness.

The processes and considerations for locally thinning an area of interest to the desired remaining silicon thickness are described.

Scanning microwave impedance microscopy is a nearfield technique using microwaves to probe the electrical properties of materials with nanoscale lateral resolution.

This is the story of how the mainstream Omniprobe FIB lift-out solution was invented and delivered to the market.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.

This article presents and evaluates a calibration method that significantly improves the spectral information that can be extracted from photon emission signals obtained from semiconductor devices. Step-by-step instructions are given for calibrating photon emission microscopes for specific measurements such as device parameters and material band gap. The article also discusses the types of errors that can occur during calibration. Although the procedure presented is used on InGaAs sensors, it applies to all common photon emission detectors.

This article describes a hardware metering fingerprint technique, called the memometer, that addresses supply chain integrity issues with field-programmable gate arrays (FPGAs). The memometer is a physically unclonable function (PUF) based on cross-coupled lookup tables that overcomes manufacturing memory power-on preset. The fingerprints are not only unique, but also reliable with average hamming distances close to the ideal values of 50% (interchip) and 0% (intrachip). Instead of having one fingerprint per device, the memometer makes provision for hundreds with the potential for more.

This article describes how physical attacks can be launched on different types of nonvolatile memory (NVM) cells using failure analysis tools. It explains how the bit information stored inside these devices is susceptible to read-out and fault injection attacks and defines vulnerability parameters to help quantify risks associated with different modalities of attack. It also presents an in-depth security analysis of emerging NVM technologies and discusses potential countermeasures.

This article, the first in a multi-part series, describes how to finely control remaining silicon thickness (RST) through the correction of mechanical surface profiles using multipoint thickness measurements. It explains why multipoint thickness measurements are necessary and discusses the realities of silicon thickness measurements. With careful processing, cleaning, and RST measurements, samples can be reliably processed to a 50 μm thickness with a variation of +/- 2.5 μm across the majority of the die.

This column describes the structure and process being followed by the councils working on the Failure Analysis Technology Roadmap at the direction of the EDFAS Board. The FA Roadmap activity was recently restructured to establish three Councils: Die-Level Roadmap Council (DLRC), Package Innovation Roadmap Council (PIRC), and an FA Future Roadmap Council (FAFRC). To incorporate a common FA workflow, the DLRC will host two separate domain teams: Isolation and Post-Isolation Domain. The column describes the FA Roadmap work conducted at the ISTFA 2022 Conference and activities planned for 2023.

This article proposes a design for a real-time Trojan detection system and explores possible solutions to the challenge of large-scale SEM image acquisition. One such solution, a deep-learning approach that generates synthetic micrographs from layout images, shows significant promise. Learning-based approaches are also used to both synthesize and classify cells. The classification outcome is matched with the design exchange format file entry to ensure the purity of the underlying IC.

Inline wafer electrical testing (WET) offers an early read on semiconductor manufacturing processes via measurements taken on test structures placed throughout the wafer. Interpreting the data can be challenging, however. In many cases, only a sample of the test sites are monitored in production. Complex manufacturing requirements further complicate the problem because some operations are iteratively executed within subregions across a given wafer, while others are run on the entire wafer at once, and still others are applied to wafers in batches. This results in a nested variance structure under which different physical mechanisms exhibit varying sensitivities to site-to-site, wafer-to-wafer, and lot-to-lot variations. This article uses Monte Carlo simulations to explore the impacts these hierarchical variance components can exert on perceptions of WET performance.

This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.