Sample preparation is a critical step for dopant profiling of FinFET devices, especially when targeting individual fins. This article describes a sample-preparation technique based on low-energy, shallow-angle ion milling and shows how it minimizes surface amorphization and improves scanning capacitance microscopy (SCM) signals representative of local active dopant concentration.

In this article, the authors evaluate micro CNC milling as an alternative to manual parallel lapping for mechanical cross-sectioning of flip-chip packaged samples. They describe both processes, and how they compare to other cross-sectioning techniques, and clearly illustrate the differences. SEM images of a manually polished sample show process-induced cracking, chipping, and delamination at the die-C4 interface. In contrast, the CNC-milled sample is artifact-free and the C4 bumps are uniformly exposed along the entire length of the cross-section.

TEM specimens prepared using a Ga FIB are susceptible to artifacts, such as surface amorphization and ion-implanted layers, that can be problematic in advanced technology nodes, particularly for FinFETs. As this article shows, however, post-FIB cleaning via concentrated argon ion milling makes for a fast and effective specimen preparation process for FinFET devices controlled to a thickness of less than 20 nm. Although the results presented here are based on 14 nm node FinFETs, the method is also applicable to the 10 and 7 nm FinFET technologies currently in production.

This article discusses the current state of large area integrated circuit deprocessing, the latest achievements in the development of automated deprocessing equipment, and the potential impact of advancements in gas-assisted etching, ion source alternatives, compact spectroscopy, and high-speed lasers.

Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.

Atomic force microscopy has been a consistent factor in the advancements of the past decade in IC nanoprobing and failure analysis. Over that time, many new atomic force measurement techniques have been adopted by the IC analysis community, including scanning conductance, scanning capacitance, pulsed current-voltage, and capacitance-voltage spectroscopy. More recently, two new techniques have emerged: diamond probe milling and electrostatic force microscopy (EFM). As the authors of the article explain, diamond probe milling using an atomic force microscope is a promising new method for in situ, localized, precision delayering of ICs, while active EFM is a nondestructive alternative to EBAC microscopy for localization of opens in IC analysis.

This paper describes a methodology for preparing contoured devices by using a milling machine in conjunction with a spectral reflectance measurement system for meeting ±5 μm remaining silicon thickness (RST) tolerances.

FIB milling is difficult if not impossible with III-V compound semiconductors and certain interconnect metals because the materials do not react well with the gallium used in most FIB systems. This article discusses the nature of the problem and explains how cryogenic FIB-SEM techniques provide a solution. It describes the basic setup of a FIB-SEM system and provides examples of its use on InN nanocrystals, GaN films, and copper-containing multilayer photovoltaic materials.

Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.

Thin film anomalies cause many device failures but they are often difficult to see. In this article, the authors explain how they found and identified an 8 to 10 nm film of tantalum causing pin shorts in a majority of ASIC modules from a particular lot. Initial attempts to delayer some of the failed modules resulted in the loss of the failure signal. It was then decided to use a focused ion beam to selectively mill through the interlayer dielectric. During milling, a secondary electron image revealed anomalous material between the fingers of a power transistor, which was subsequently identified as tantalum. Such defects, as the authors explain, are common in damascene processes when materials are not properly removed during etching.