Xenon plasma focused ion beam specimen preparation is ideal for preparing plan view TEM specimens due to its large-volume-milling capabilities. This article describes concentrated Ar ion beam milling using low energy as a post-pFIB final thinning step of plan view TEM specimens from a phase change memory device. Precise control of specimen thinning is achieved, which results in high-quality specimens with pristine surfaces and a large field of view for TEM characterization.

Broad ion beam delayering is a versatile technique for whole-chip failure analysis. The large area of uniformity coupled with the ability to precisely stop at the layer of interest facilitates repeatable, rapid defect detection anywhere on the chip.

This article provides an introduction to focused ion beam (FIB) circuit editing, covering the basic process along with best practices and procedures.

The processes and considerations for locally thinning an area of interest to the desired remaining silicon thickness are described.

This is the story of how the mainstream Omniprobe FIB lift-out solution was invented and delivered to the market.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.

This article, the first in a multi-part series, describes how to finely control remaining silicon thickness (RST) through the correction of mechanical surface profiles using multipoint thickness measurements. It explains why multipoint thickness measurements are necessary and discusses the realities of silicon thickness measurements. With careful processing, cleaning, and RST measurements, samples can be reliably processed to a 50 μm thickness with a variation of +/- 2.5 μm across the majority of the die.

Sample preparation is a critical step for dopant profiling of FinFET devices, especially when targeting individual fins. This article describes a sample-preparation technique based on low-energy, shallow-angle ion milling and shows how it minimizes surface amorphization and improves scanning capacitance microscopy (SCM) signals representative of local active dopant concentration.

This article discusses the failure analysis challenges associated with large overmolded 2.5D packages and explains how laser decapsulation followed by microwave-induced plasma (MIP) spot etching removes overmold while keeping everything else intact. It also describes a defect isolation procedure in which the sample is analyzed in a large chamber environmental SEM with its ball grid array directly wired to an EBAC amplifier.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

This Master FA Technique column describes an easy and inexpensive solution to the problem of preparing TEM cross-sectional samples from etched wafers with large aspect ratio vias.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.

Several failure analysis case studies have been conducted over the past few years, illustrating the importance of preserving root-cause evidence by means of artifact-free decapsulation. The findings from three of those studies are presented in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also includes images that compare the results of different decapsulation methods.

Three case studies involving 14 nm SRAM technology show how progressive FIB cross-sectioning and top-down analysis can be supplemented with nanoprobing and TEM tomography to determine the root cause of failure. In the first case, the memory failure is traced to an abnormal gate profile. In the second case, the failure is attributed to a metal line short, and in the third case, a gate defect.

The causes of failure in flip-chip packaged devices are often found at the interface between the die and package. Exposing the site of interest usually entails some form of mechanical cross-sectioning with the sample embedded in an epoxy puck. This article brings attention to some of the drawbacks with the current approach and presents a solution in the form of a redesigned puck. As test results show, the new puck significantly reduces polishing time, and when cast with a conductive epoxy, minimizes charging artifacts and image distortion during SEM analysis. It also facilitates easy sample removal for subsequent analysis.

In this article, the authors evaluate micro CNC milling as an alternative to manual parallel lapping for mechanical cross-sectioning of flip-chip packaged samples. They describe both processes, and how they compare to other cross-sectioning techniques, and clearly illustrate the differences. SEM images of a manually polished sample show process-induced cracking, chipping, and delamination at the die-C4 interface. In contrast, the CNC-milled sample is artifact-free and the C4 bumps are uniformly exposed along the entire length of the cross-section.

TEM specimens prepared using a Ga FIB are susceptible to artifacts, such as surface amorphization and ion-implanted layers, that can be problematic in advanced technology nodes, particularly for FinFETs. As this article shows, however, post-FIB cleaning via concentrated argon ion milling makes for a fast and effective specimen preparation process for FinFET devices controlled to a thickness of less than 20 nm. Although the results presented here are based on 14 nm node FinFETs, the method is also applicable to the 10 and 7 nm FinFET technologies currently in production.

This article discusses the current state of large area integrated circuit deprocessing, the latest achievements in the development of automated deprocessing equipment, and the potential impact of advancements in gas-assisted etching, ion source alternatives, compact spectroscopy, and high-speed lasers.

Liquid metal ion and plasma beam FIB systems are widely used in the semiconductor industry for TEM lamella preparation, circuit edit, and cross-sectional analysis. This article compares the deprocessing capability of a Ga FIB with that of a Xe plasma FIB. Both systems were used to delayer an Intel 14 nm processor from M8 down to the transistor contacts. As the images in the article show, a 100 × 100 µm window was opened by the Xe plasma FIB and a 20 × 20 µm window was opened with the Ga FIB. Related issues such as processing time, end point detection, and surface roughness are also discussed.