This article discusses the application of near infrared (IR) microscopy in silicon photonic failure analysis. It explains how this technique helps isolate unexpected light losses in photonic integrated circuits (PICs). The paper outlines the experimental setup for IR microscopy and presents three case studies demonstrating its effectiveness: detecting packaging failures through comparative analysis with known good samples; identifying in-operation failures, particularly permanent damage in silicon-based spot size converters due to two-photon absorption at high power levels; and locating yield detractors in optical paths.

This article describes a proposed novel metric to furnish chip designers with a prognostic tool for x-ray imaging in the pre-silicon stage. This metric is fashioned to provide designers with a concrete measure of how visible the fine-pitched features of their designs are under x-ray inspection. It utilizes a combination of x-ray image data collection, analysis, and simulations to evaluate different design elements.

This column is part of a series of reports on the findings to date of the EDFAS Failure Analysis Roadmap Councils. The Failure Analysis Future Roadmap Council (FAFRC) is concerned with identifying the longer term needs of the FA community. This article discusses analysis challenges associated with the growing number of elements being incorporated into integrated circuit fabrication. It includes tables summarizing top challenges in front end and package analysis.

The Package Innovation Roadmap Council (PIRC) was established as part of the Failure Analysis Technology Roadmap activity at the direction of the EDFAS Board. This column provides an overview of a technical paper by the PIRC that highlights recent innovations, technology gaps, and future development trends in package fault isolation and failure analysis. The paper focuses on three main categories: 1) Artificial intelligence (AI) applications, 2) Sample handling, and 3) FA tool robustness.

This article, the first in a multi-part series, describes how to finely control remaining silicon thickness (RST) through the correction of mechanical surface profiles using multipoint thickness measurements. It explains why multipoint thickness measurements are necessary and discusses the realities of silicon thickness measurements. With careful processing, cleaning, and RST measurements, samples can be reliably processed to a 50 μm thickness with a variation of +/- 2.5 μm across the majority of the die.

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.

This editorial discusses the emergence of chiplets and its potential impact on IC design, fabrication, and failure analysis.

This article discusses the failure analysis challenges associated with large overmolded 2.5D packages and explains how laser decapsulation followed by microwave-induced plasma (MIP) spot etching removes overmold while keeping everything else intact. It also describes a defect isolation procedure in which the sample is analyzed in a large chamber environmental SEM with its ball grid array directly wired to an EBAC amplifier.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

Several failure analysis case studies have been conducted over the past few years, illustrating the importance of preserving root-cause evidence by means of artifact-free decapsulation. The findings from three of those studies are presented in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also includes images that compare the results of different decapsulation methods.

Modified Talbot X-ray interferometry provides three contrast modes simultaneously: absorption, phase, and dark field/scattering. This article describes the powerful new imaging technique and shows how it is used to characterize various types of defects in advanced semiconductor packages.

Scanning acoustic tomography (SAT) is widely used to detect defects such as voids and delamination in electronic devices. In this article, the authors explain how they improved the spatial resolution and detection sensitivity of SAT by switching from a conventional piezoelectric probe to a capacitive micromachined ultrasound transducer (CMUT) and by using pulse compression signal processing. They also present examples showing how the improvement makes it possible to detect very small defects in multilayer stacks and BGA packages whether in through-transmission or reflection imaging mode.

The causes of failure in flip-chip packaged devices are often found at the interface between the die and package. Exposing the site of interest usually entails some form of mechanical cross-sectioning with the sample embedded in an epoxy puck. This article brings attention to some of the drawbacks with the current approach and presents a solution in the form of a redesigned puck. As test results show, the new puck significantly reduces polishing time, and when cast with a conductive epoxy, minimizes charging artifacts and image distortion during SEM analysis. It also facilitates easy sample removal for subsequent analysis.

This article describes a form of lock-in thermography that achieves 3D localization of thermally active defects in stacked die packages. In this approach, phase shifts associated with thermal propagation delay are analyzed as a function of frequency. This allows for a precise localization of defects in all three spatial dimensions and can serve as a guide for subsequent high-resolution physical analyses.

In this article, the authors evaluate micro CNC milling as an alternative to manual parallel lapping for mechanical cross-sectioning of flip-chip packaged samples. They describe both processes, and how they compare to other cross-sectioning techniques, and clearly illustrate the differences. SEM images of a manually polished sample show process-induced cracking, chipping, and delamination at the die-C4 interface. In contrast, the CNC-milled sample is artifact-free and the C4 bumps are uniformly exposed along the entire length of the cross-section.

Using the example of smart card radio frequency identification (RFID) devices, this article examines electrostatic discharge risk scenarios encountered during assembly and in the field, and outlines basic countermeasures.

Electro optical terahertz pulse reflectometry (EOTPR) is a nondestructive fault isolation technique that is well suited for today’s ICs. This article provides examples of how EOTPR is being used to investigate 2.5D and 3D packages, wafer level fanout packages, and MEMS devices. It also discusses recent advancements in EOTPR systems and software.

IBM engineers recently conducted a study to better understand and control the reliability of copper pillar solder joints in 2.5-D packages. Here they describe their approach and the results they obtained. They explain how they created test samples to evaluate different solder compositions, pillar geometries, and thermal histories and assess their effect on microstructure, precipitate morphology, intermetallic layer thickness, and shear strength. They also present thermal cycling test results comparing the performance of silicon and glass interposers.

This is the second article in a two-part series investigating solder connection failures associated with BGA packages. Part I, in the February 2017 issue of EDFA, examines various cases of open and short circuit failures, discusses the formation of voids, and explains how to reveal important clues by grinding away the BGA package. Part II continues the analysis of voids and focuses in on failures due to circuit board faults. In such cases, the board is ground away from the backside, stopping just short of the first inner copper layer. The alignment of the two uppermost copper layers, the integrity of microvias, and other potential problems are then examined using polarized light which readily passes through the remaining resin and fibers. As the examples in the article show, this approach can reveal a wide range of manufacturing defects in PCBs.

This article is the first in a two-part series analyzing solder connection failures between BGA packages and PCB assemblies. Part I examines failures attributed to oxygen intrusion during reflow, underetched solder resist, and solder paste printing problems. In the latter case, X-ray inspection revealed no abnormalities other than a variation in ball size. To get to the root cause, the corpus of the BGA was progressively ground away, leaving only the balls and an unobstructed view of the PCB surface. A description of the process, supported by detailed images, is included in the article. In Part II, scheduled for the May 2017 issue of EDFA, the author delves deeper into the analysis of voids and presents an alternate FA approach that involves grinding away much of the PCB.