A deep learning-based nondestructive approach for void segmentation in BGA solder balls using 3D x-ray microscopy is presented.

The influence of electric current flow and electrically induced Joule heat on thermal stress for weld joint cracks at both interfaces is still not fully comprehended. This article investigates the effect of subjecting the ball grid array package to a cyclic current input. Current density, Joule effect, and temperature curves are examined.

In this case study, the author describes the investigation of a defective DC-DC converter retrieved from an aircraft following the report of abnormal system behavior. Electrical testing, local probing, X-ray imaging, and cross-sectional analysis led to the discovery of cracks on several pins and in some of the solder material. The cracks were caused by different rates of thermal expansion and were remedied with the help of thermomechanical analysis, EBSD imaging, and phase map comparisons for thick and thin solder joints.

This is the second article in a two-part series investigating solder connection failures associated with BGA packages. Part I, in the February 2017 issue of EDFA, examines various cases of open and short circuit failures, discusses the formation of voids, and explains how to reveal important clues by grinding away the BGA package. Part II continues the analysis of voids and focuses in on failures due to circuit board faults. In such cases, the board is ground away from the backside, stopping just short of the first inner copper layer. The alignment of the two uppermost copper layers, the integrity of microvias, and other potential problems are then examined using polarized light which readily passes through the remaining resin and fibers. As the examples in the article show, this approach can reveal a wide range of manufacturing defects in PCBs.

This article is the first in a two-part series analyzing solder connection failures between BGA packages and PCB assemblies. Part I examines failures attributed to oxygen intrusion during reflow, underetched solder resist, and solder paste printing problems. In the latter case, X-ray inspection revealed no abnormalities other than a variation in ball size. To get to the root cause, the corpus of the BGA was progressively ground away, leaving only the balls and an unobstructed view of the PCB surface. A description of the process, supported by detailed images, is included in the article. In Part II, scheduled for the May 2017 issue of EDFA, the author delves deeper into the analysis of voids and presents an alternate FA approach that involves grinding away much of the PCB.

This article explains how the failure of a high-voltage capacitor led to the discovery of an unusual defect. Testing showed that the capacitor shorted due to silver migration, which investigators believe was facilitated by voids in the dielectric that had been present from the time of manufacture. Through some combination of time, electric potential, trapped humidity, and elevated operating temperature, plate material migrated into the voids, creating a short path that led to the failure. Using acoustic images as a guide, the failed capacitor was cross-sectioned, allowing investigators to examine the voids more closely and thereby confirm their theory.

Stress voiding has re-emerged as a concern in advanced metal systems with their reduced dimensions and multilayer designs. Unless analysts are familiar with the physics and history of stress voids in ICs, chances are they will go unnoticed. This article discusses the basic cause of stress cracks and the clues that give them away.

Electronic components and assemblies are subjected to temperature variations at every stage of life, resulting in the buildup of internal stress. This article explains how such stress contributes to failures and introduces a measurement technique that allows users to visualize stress distributions and assess their effects on lifetime and reliability. Application examples illustrating the capabilities of the new topography and deformation measurement approach are also presented.

Layout sensitivity, a measure of vulnerability to yield loss, typically takes several days to compute for a modern VLSI design. In this article, the authors present and demonstrate a new stochastic model that can significantly expedite the process. The model is based on simple IC layout parameters including wire width, wire spacing, and channel density. The authors explain how they derived the model and how it compares to actual data. They also discuss the causes and effects of open and short defects and define the concepts of critical area and layout sensitivity.

Parametric failures are of two general types. One type is due to defects that affect circuit parameters. The other type, which occurs in defect-free parts, is the result of interdie parameter statistical variation. IC failures can be caused by variations in any number of parameters including L eff , W eff , I Dsat , V t , contact resistance, effective gate oxide thickness, source and drain resistance, interconnect sheet resistance, and intrametal spacing affecting cross-talk, ground bounce noise, and IR voltage drops. These failures often influence the maximum operating frequency of the IC and are seldom detected by simple stuck-at fault, delay fault, functional, or I DDQ tests. This article discusses the origin, classification, and detection of a wide range of parametric failures.

Resistive interconnections, a type of soft failure, are extremely difficult to find using existing backside methods, and with flip-chip packages, alternative front side approaches are of little or no help. In an effort to address this challenge, a team of engineers developed a new method that uses the effects of resistive heating to directly locate defective vias, contacts, and conductors from either side of the die. In this article, they discuss the basic principles of their new method and demonstrate its use on two ICs in which a variety of resistive interconnection failures were found.

CMOS IC failure mechanisms are of three general types: bridge defects, open circuit defects, and parametric related failures. This article summarizes bridge and open-circuit defect properties and provides references for further self-study. Bridge defects are characterized based on location, their significance in terms of logic gates and transistors, and critical resistance for dc logic and timing failures. Open defects are more complex and diverse with six possible failure modes each of which are described in the article.

Picosecond imaging circuit analysis (PICA) is an advanced diagnostic technique that measures device switching activity on CMOS ICs through the backside of the die. Due to its relatively large field of view, it can quickly locate defects among large numbers of candidates. In this case study, the authors explain how they used PICA to identify a particular I/O circuit defect on the IBM System/390 G5 microprocessor. They also explain how they verified the diagnostic result using circuit simulations.

Unit level traceability (ULT) is a powerful tool that allows complete die histories to be accessed in the course of testing and analysis. It is especially useful for identifying the likely causes of microprocessor failures and in cases where failure analysis resources are limited. In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus control. Another failure, observed after burn-in, was traced to the presence of residual titanium left after metal etch.

This case study describes the difficulties and challenges failure analysts encountered in their nearly year-long investigation into the cause of cracking in a dielectric film. Despite the trend in microelectronics to use ever more costly and sophisticated equipment, this investigation was conducted using only SEM and optical microscope observations coupled with persistent detective work, which eventually uncovered to the cause.