Parametric analysis of SRAM cells is widely used to locate faults and analyze device failures, but the pico-probing and bit-line multiplexing required for data acquisition is becoming increasingly difficult. This article explains how the addition of an on-die low-yield analysis circuit eliminates the problem. The simplicity of the measurement circuit and the potential to use a known library of curves, makes low-yield analysis one of the most versatile DFT techniques for cache fault isolation.
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