Scan-based diagnostics produce high-confidence target lists of suspected faults associated with electrical fail signatures. Physical coordinates extracted from these lists serve as a guide for physical failure analysis. When certain conditions are met for the design database and pattern sets, the extraction can be automated and the analysis completed within minutes. The logic mapping flow is a natural extension of scan-based diagnosis with the potential to reach new levels of electrical failure analysis without the extensive data collection and resources associated with signature analysis. This article describes the logic mapping concept and how to implement the flow. It also presents the results of actual cases in which logic mapping was used.