Abstract
This column discusses the benefits of using IC design and wafer-processing test data for failure analysis.
Copyright © ASM International® 2017
2017
ASM International
You do not currently have access to this content.
Rao Desineni, Yan Pan; Speeding Up Failure Analysis Using Fab and Design Data. EDFA Technical Articles 1 November 2017; 19 (4): 62–63. doi: https://doi.org/10.31399/asm.edfa.2017-4.p062
Download citation file:
This column discusses the benefits of using IC design and wafer-processing test data for failure analysis.